FPGA Cameralink图像生成模板，Cameralink采集卡图像采集。
1：采集卡安装
2：FPGA产生图像模板
module vga_lcd_driver(
input clk,
input [7:0] r_i,
input [7:0] g_i,
input [7:0] b_i,
output [7:0] r_o,
output [7:0] g_o,
output [7:0] b_o,
output de,
output vsync,
output hsync
);
reg [11:0] hcounter;
reg [11:0] vcounter;
// Colours converted using The RGB
//-- Set the video mode to 1920x1080x60Hz (150MHz pixel clock needed)
parameter hVisible = 1920;
parameter hStartSync = 1920+88;
parameter hEndSync = 1920+88+44;
parameter hMax = 1920+88+44+148; //2200
parameter vVisible = 1080;
parameter vStartSync = 1080+4;
parameter vEndSync = 1080+4+5;
parameter vMax = 1080+4+5+36; //1125
//-- Set the video mode to 1440x900x60Hz (106.47MHz pixel clock needed)
//-- Set the video mode to 640x480x60Hz (25MHz pixel clock needed)
//------------------------------------------
//v_sync counter & generator
always@(posedge clk) begin
if(hcounter < hMax - 12'd1) //line over
hcounter <= hcounter + 12'd1;
else
hcounter <= 12'd0;
end
always@(posedge clk) begin
if(hcounter == hMax - 12'd1) begin
if(vcounter < vMax - 12'd1) //frame over
vcounter <= vcounter + 12'd1;
else
vcounter <= 12'd0;
end
end
assign hsync = ((hcounter >= (hStartSync - 2'd2))&&(hcounter < (hEndSync - 2'd2)))? 1'b0:1'b1; //Generate the hSync Pulses
assign vsync = ((vcounter >= (vStartSync - 1'b1))&&(vcounter < (vEndSync - 1'b1)))? 1'b0:1'b1; //Generate the vSync Pulses
assign de = (vcounter >= vVisible || hcounter >= hVisible) ? 1'b0 : 1'b1;
assign r_o = r_i;
assign g_o = g_i;
assign b_o = b_i;
endmodule
3：FPGA数据封装
将图像模板，封装成LVDS时序，发送出去。送至采集卡进行采集。
4：采集卡设置
设置采集卡分辨率1920X1080。
5：电脑上位机采集效果
