前言

进行 FPGA 全加器 实验

一、实验原理

module adder(ain,bin,cin,cout,s);
input ain,bin,cin;
output cout,s;
assign cout=ain&bin | ain&cin | bin&cin;
assign s=ain^bin^cin;
endmodule




`timescale 1ns/1ns
module adder_tst();
reg ain,bin,cin;
wire cout,s;
initial begin
ain=1'b0;bin=1'b0;cin=1'b0;
#20 ain=1'b0;bin=1'b0;cin=1'b1;
#20 ain=1'b0;bin=1'b1;cin=1'b0;
#20 ain=1'b0;bin=1'b1;cin=1'b1;
#20 ain=1'b1;bin=1'b0;cin=1'b0;
#20 ain=1'b1;bin=1'b0;cin=1'b1;
#20 ain=1'b1;bin=1'b1;cin=1'b0;
#20 ain=1'b1;bin=1'b1;cin=1'b1;
end
adder u0(.ain(ain),
      .bin(bin),
      .cin(cin),
      .cout(cout),
      .s(s));
endmodule



module adder4(ain,bin,cin,s,cout);
input[3:0] ain,bin;
input cin;
output[3:0] s;
output cout;
wire cout1,cout2,cout3;
adder u0(.ain(ain[0]),
      .bin(bin[0]),
      .cin(cin),
      .cout(cout1),
      .s(s[0]));
adder u1(.ain(ain[1]),
      .bin(bin[1]),
      .cin(cout1),
      .cout(cout2),
      .s(s[1]));
adder u2(.ain(ain[2]),
      .bin(bin[2]),
      .cin(cout2),
      .cout(cout3),
      .s(s[2]));
adder u3(.ain(ain[3]),
      .bin(bin[3]),
      .cin(cout3),
      .cout(cout),
      .s(s[3]));
endmodule

二、实验过程

三、实验结果

参考文献

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