设计内容：
实现UART及实时系统完成收发UART操作的测试系统，要求如下：

本工程包括一个测试系统，UART.
UART包括baud波特率模块、UART的transfer and receive模块等

1 Objective
The objective of this project is to design and build a complete UART in VHDL.
Upon completion, the student must be able to:
• Design, realize and test transmitter and receiver modules;
• Design, realize and test a baud rate generator;
• Demonstrate a complete understanding for the design of a UART and its
interface in a real-time system.

工程截图：

顶层代码：

librar