一起学习用Verilog在FPGA上实现CNN----(四)池化层设计

news2024/12/30 4:51:34

1 池化层设计

自顶而下分析池化层的设计过程

1.1 Average Pool Multi Layer

图为该项目的平均池化层，其包含一个AvgPoolSingle单元，模块的输入为图像特征矩阵，输出为池化后的特征矩阵

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图片来自附带的技术文档《Hardware Documentation》

池化层的原理图如图所示，其中输入位宽为75264，输出位宽为18816。池化层位于卷积层和激活层之后，第一次卷积层输出位宽为75264，因此池化层的输入位宽为75264。Average Pool Multi Layer的深度为6，前卷积层的输出特征H和W均为28，故输入位宽为28x28x6x16=75264；平均池化窗口大小为2x2，输出特征H和W变为14，输出位宽为14x14x6x16=18816

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1.2 Average Pool Single Layer

该单元是执行单个通道的平均池化操作，由多个AvgU组成，如图所示：

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图片来自附带的技术文档《Hardware Documentation》

原理图如图所示，该单元输入位宽为12544，输出位宽为3136。前一层卷积输出特征H为28，W为28，Average Pool Single Layer的深度为1，因此输入位宽为28x28x1x16=12544；该项目平均池化的窗口大小为2x2，故输出位宽为14x14x1x16=3136

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1.3 Averaging Unit

Averaging Unit如图所示，求输入4个数的均值。该单元先求4个数A、B、C、D的和，再将和乘以0.25得到4个数的均值

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图片来自附带的技术文档《Hardware Documentation》

原理图如图所示，输入为4个位宽16的数，输出为位宽16的均值

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2 代码实现

2.1 AvgUnit

2.1.1 设计输入

创建AvgUnit文件，操作如图：

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输入文件名：

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确认创建：

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双击打开，输入代码：

module AvgUnit (numA,numB,numC,numD,AvgOut);
  
parameter DATA_WIDTH = 16;

input [DATA_WIDTH-1:0] numA,numB,numC,numD;
output [DATA_WIDTH-1:0] AvgOut;

wire [DATA_WIDTH-1:0] add1result;
wire [DATA_WIDTH-1:0] add2result;
wire [DATA_WIDTH-1:0] add3result;
reg [DATA_WIDTH-1:0] quarter = 16'b0011010000000000;

floatAdd16 FADD1 (numA,numB,add1result);
floatAdd16 FADD2 (add1result,numC,add2result);
floatAdd16 FADD3 (add2result,numD,add3result);  
floatMult16 FM (add3result,quarter,AvgOut);  
endmodule

如图所示：

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2.1.2 分析与综合

将AvgUnit设置为顶层：

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对设计进行分析，操作如图：

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分析后的设计，Vivado自动生成原理图，如图：

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AvgUnit原理图如图：

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对设计进行综合，操作如图：

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综合完成，关闭即可：

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2.1.3 功能仿真

创建TestBench，操作如图所示：

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输入激励文件名tb_AvgUnit：

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双击打开，输入激励代码：

`timescale 1ns / 1ps
module tb_AvgUnit();
reg [15:0] numA;
reg [15:0] numB;
reg [15:0] numC;
reg [15:0] numD;
wire [15:0] AvgOut;

initial begin
	
	// Avg(2,3,4,5) = 3.5
	#0
  numA = 16'h4000;
  numB = 16'h4200;
  numC = 16'h4400;
  numD = 16'h4500;

	// Avg(1,2,3,4) = 2.5
	#10
	numA = 16'h3C00;
  numB = 16'h4000;
  numC = 16'h4200;
  numD = 16'h4400;
	
	// Avg(-1,-2,-3,-4) = -2.5
	#10
	numA = 16'hBC00;
  numB = 16'hC000;
  numC = 16'hC200;
  numD = 16'hC400;
  
  // Avg(-2,-3,-4,-5) = 3.5
  #10
	numA = 16'hC000;
  numB = 16'hC200;
  numC = 16'hC400;
  numD = 16'hC500;
  #10
	$stop;
end

AvgUnit UUT
(
    .numA(numA),
    .numB(numB),
    .numC(numC),
    .numD(numD),
    .AvgOut(AvgOut)
);

endmodule

如图所示：

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将tb_AvgUnit设置为顶层：

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开始进行仿真，操作如下:

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开始仿真，如图：

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仿真波形，如图所示：

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仿真结束，关闭仿真：

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2.2 AvgPoolSingle

2.2.1 设计输入

创建AvgPoolSingle文件，如图：

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双击打开，输入代码：

module AvgPoolSingle(aPoolIn,aPoolOut);
  
parameter DATA_WIDTH = 16;
parameter InputH = 28;
parameter InputW = 28;
parameter Depth = 1;

input [0:InputH*InputW*Depth*DATA_WIDTH-1] aPoolIn;
output [0:(InputH/2)*(InputW/2)*Depth*DATA_WIDTH-1] aPoolOut;

genvar i,j;

generate  // 2x2的池化窗口 
  for (i=0; i<(InputH); i=i+2) begin
    for (j=0; j<(InputW); j=j+2) begin
    AvgUnit
    #(
     .DATA_WIDTH(DATA_WIDTH)
     )
     AU
    (
      .numA(aPoolIn[(i*InputH+j)*DATA_WIDTH+:DATA_WIDTH]),
      .numB(aPoolIn[(i*InputH+j+1)*DATA_WIDTH+:DATA_WIDTH]),
      .numC(aPoolIn[((i+1)*InputH+j)*DATA_WIDTH+:DATA_WIDTH]),
      .numD(aPoolIn[((i+1)*InputH+j+1)*DATA_WIDTH+:DATA_WIDTH]),
      .AvgOut(aPoolOut[(i/2*InputH/2+j/2)*DATA_WIDTH+:DATA_WIDTH])
      );
    end
  end
endgenerate
endmodule

如图所示：

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2.2.2 分析与综合

将AvgPoolSingle文件设置为顶层：

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关闭上次的分析文件：

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对本次设计进行分析，操作如图：

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分析后的设计，Vivado自动生成原理图，如图：

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该模块由多个AvgUnit组成，如图：

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对设计进行综合，操作如图：

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综合完成，关闭即可：

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2.2.3 功能仿真

创建TestBench，操作如图所示：

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双击打开，输入激励代码：

`timescale 1ns / 1ps
module tb_AvgPoolSingle();
reg [28*28*16-1:0] inAvg;
wire [14*14*16-1:0] outAvg;

initial begin
    #0
    inAvg = 12544'h4000440040004400400044004000440040004400400044004000440040004400400044004000440040004400400044004000440040004400450042004500420045004200450042004500420045004200450042004500420045004200450042004500420045004200450042004500420040004400400044004000440040004400400044004000440040004400400044004000440040004400400044004000440040004400400044004500420045004200450042004500420045004200450042004500420045004200450042004500420045004200450042004500420045004200400044004000440040004400400044004000440040004400400044004000440040004400400044004000440040004400400044004000440045004200450042004500420045004200450042004500420045004200450042004500420045004200450042004500420045004200450042004000440040004400400044004000440040004400400044004000440040004400400044004000440040004400400044004000440040004400450042004500420045004200450042004500420045004200450042004500420045004200450042004500420045004200450042004500420040004400400044004000440040004400400044004000440040004400400044004000440040004400400044004000440040004400400044004500420045004200450042004500420045004200450042004500420045004200450042004500420045004200450042004500420045004200400044004000440040004400400044004000440040004400400044004000440040004400400044004000440040004400400044004000440045004200450042004500420045004200450042004500420045004200450042004500420045004200450042004500420045004200450042004000440040004400400044004000440040004400400044004000440040004400400044004000440040004400400044004000440040004400450042004500420045004200450042004500420045004200450042004500420045004200450042004500420045004200450042004500420040004400400044004000440040004400400044004000440040004400400044004000440040004400400044004000440040004400400044004500420045004200450042004500420045004200450042004500420045004200450042004500420045004200450042004500420045004200400044004000440040004400400044004000440040004400400044004000440040004400400044004000440040004400400044004000440045004200450042004500420045004200450042004500420045004200450042004500420045004200450042004500420045004200450042004000440040004400400044004000440040004400400044004000440040004400400044004000440040004400400044004000440040004400450042004500420045004200450042004500420045004200450042004500420045004200450042004500420045004200450042004500420040004400400044004000440040004400400044004000440040004400400044004000440040004400400044004000440040004400400044004500420045004200450042004500420045004200450042004500420045004200450042004500420045004200450042004500420045004200400044004000440040004400400044004000440040004400400044004000440040004400400044004000440040004400400044004000440045004200450042004500420045004200450042004500420045004200450042004500420045004200450042004500420045004200450042004000440040004400400044004000440040004400400044004000440040004400400044004000440040004400400044004000440040004400450042004500420045004200450042004500420045004200450042004500420045004200450042004500420045004200450042004500420040004400400044004000440040004400400044004000440040004400400044004000440040004400400044004000440040004400400044004500420045004200450042004500420045004200450042004500420045004200450042004500420045004200450042004500420045004200;
    #10
    $stop;
end
AvgPoolSingle UUT
  (
    .aPoolIn(inAvg),
    .aPoolOut(outAvg)
  );
endmodule

如图所示：

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将tb_AvgPoolSingle设置为顶层：

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开始进行仿真，操作如图：

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如图，开始仿真：

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仿真波形，如图：

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仿真完成，关闭仿真：

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2.3 AvgPoolMulti

2.3.1 设计输入

创建AvgPoolMulti文件，如图：

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双击打开，输入代码：

module AvgPoolMulti(clk, reset, apInput, apOutput);

parameter DATA_WIDTH = 16;
parameter D = 6;
parameter H = 28;
parameter W = 28;

input reset,clk;
input [0:H*W*D*DATA_WIDTH-1] apInput;
output reg [0:(H/2)*(W/2)*D*DATA_WIDTH-1] apOutput;

reg [0:H*W*DATA_WIDTH-1] apInput_s;
wire [0:(H/2)*(W/2)*DATA_WIDTH-1] apOutput_s;
integer counter;


AvgPoolSingle
  #(
      .DATA_WIDTH(DATA_WIDTH),
      .InputH(H),
      .InputW(W)
  ) AvgPool
  (
      .aPoolIn(apInput_s),
      .aPoolOut(apOutput_s)
  );

always @ (posedge clk or posedge reset) begin
  if (reset == 1'b1) begin
    counter = 0;
  end
  else if (counter<D) begin 
    counter = counter+1;
  end
end

always @ (*) begin
  apInput_s = apInput[counter*H*W*DATA_WIDTH+:H*W*DATA_WIDTH];
  apOutput[counter*(H/2)*(W/2)*DATA_WIDTH+:(H/2)*(W/2)*DATA_WIDTH] = apOutput_s;
end

endmodule

如图所示：

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将AvgPoolMulti设置为顶层：

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2.3.2 分析与综合

对设计进行分析，操作如图：

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分析后的设计，Vivado自动生成原理图，如图：

在这里插入图片描述

原理图如图所示：

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对设计进行综合，操作如图：

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2.3.3 功能仿真

创建TestBench，操作如图所示：

在这里插入图片描述
双击打开，输入激励代码：

`timescale 1ns / 1ps
module tb_AvgPoolMulti();
reg clk,reset;
reg [6*28*28*16-1:0] inAvg;
wire [6*14*14*16-1:0] outAvg;

localparam PERIOD = 100;

integer i;

always
	#(PERIOD/2) clk = ~clk;
	
initial begin
    #0
    clk = 1'b0;
	  reset = 1;
    inAvg = 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    #(PERIOD)
	  reset = 0;
    #(8*PERIOD)
    for (i = 6*14*14-1; i >=0; i = i - 1) begin
		  $displayh(outAvg[i*16+:16]);
	  end
    $stop;
end
AvgPoolMulti UUT
  (
    .clk(clk),
    .reset(reset),
    .apInput(inAvg),
    .apOutput(outAvg)
  );
endmodule

如图所示：

在这里插入图片描述
将tb_AvgPoolMulti设置为顶层：

在这里插入图片描述

开始进行仿真，操作如下:

在这里插入图片描述

如图，开始仿真：

在这里插入图片描述

仿真波形，如图所示：

在这里插入图片描述

仿真结束，关闭仿真：

在这里插入图片描述

2.4 IntegrationConv

2.4.1 设计输入

双击打开integrationConv文件，修改代码为：

module integrationConv (clk,reset,CNNinput,Conv1F,Conv2F,iConvOutput);

parameter DATA_WIDTH = 16;
parameter ImgInW = 32;
parameter ImgInH = 32;
parameter Conv1Out = 28;
parameter AvgP1out = 14;
parameter Conv2Out = 10;
parameter Kernel = 5;
parameter AvgP2out = 5;
parameter DepthC1 = 6;
parameter DepthC2 = 16;


input clk, reset;
input [ImgInW*ImgInH*DATA_WIDTH-1:0] CNNinput;
input [Kernel*Kernel*DepthC1*DATA_WIDTH-1:0] Conv1F;
input [DepthC2*Kernel*Kernel*DepthC1*DATA_WIDTH-1:0] Conv2F;
output [DepthC2*DATA_WIDTH-1:0] iConvOutput;

reg C1rst,AP1rst,Tanh1Reset;
wire Tanh1Flag;

wire [Conv1Out*Conv1Out*DepthC1*DATA_WIDTH-1:0] C1out;
wire [Conv1Out*Conv1Out*DepthC1*DATA_WIDTH-1:0] C1outTanH;

wire [AvgP1out*AvgP1out*DepthC1*DATA_WIDTH-1:0] AP1out;

convLayerMulti C1
(
	.clk(clk),
	.reset(reset),
	.image(CNNinput),
	.filters(Conv1F),
	.outputConv(C1out)
);

UsingTheTanh16
#(.nofinputs(Conv1Out*Conv1Out*DepthC1))
Tanh1(
      .x(C1out),
      .clk(clk),
      .Output(C1outTanH),
      .resetExternal(Tanh1Reset),
      .FinishedTanh(Tanh1Flag)
      );

AvgPoolMulti AP1
  (
    .clk(clk),
    .reset(reset),
    .apInput(C1outTanH),
    .apOutput(AP1out)
  );
convLayerMulti
#(
  .DATA_WIDTH(16),
  .D(6),
  .H(14),
  .W(14),
  .F(5),
  .K(16)
) C2 
(
	.clk(clk),
	.reset(reset),
	.image(AP1out),
	.filters(Conv2F),
	.outputConv(iConvOutput)
);
endmodule

如图所示：

在这里插入图片描述

将integrationConv设置为顶层：

在这里插入图片描述

关闭上次的分析文件：

在这里插入图片描述

2.4.2 分析与综合

对设计进行分析，操作如图：

在这里插入图片描述

分析后的设计，Vivado自动生成原理图，如图：

在这里插入图片描述

顶层原理图，如图所示：

在这里插入图片描述

对设计进行综合，操作如图：

在这里插入图片描述

希望本文对大家有帮助，上文若有不妥之处，欢迎指正

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