目录
1. 简介
2. 默认接口实现
2.1 执行模式
2.2 接口范式
2.2.1 存储器
2.2.2 串流
2.3.3 寄存器
2.3 Vitis Kernel Flow
2.3.1 默认的协议
2.3.2 vadd 代码
2.3.3 查看报告
2.4 Vivado IP Flow
2.4.1 默认的协议
2.4.2 vadd 代码
2.4.3 查看报告
3. 测试与波形
3.1 TestBench
3.2 理解控制协议
3.3 Wave Viewer
3.3.1 整体波形
3.3.2 ap_ctrl 信号
4. 模块拆分
4.1 分析
4.2 compute_add
4.2 IP 图
5. 总结
1. 简介
本文总结 HLS 块级控制协议，包括以下内容：
- 执行模式
- 重叠模式
- 顺序模式
- 自动重启模式
- 接口范式
- 存储器
- 串流
- 寄存器
- 对比 Vitis Kernel Flow 与 Vivado IP Flow 示例
- 了解 Wave Viewer 中的波形
原示例：
https://github.com/Xilinx/Vitis_Accel_Examples/tree/main/hello_world
https://github.com/Xilinx/Vitis_Accel_Examples/tree/main/hello_world
2. 默认接口实现
2.1 执行模式
1）Vitis kernel 或 Vivado IP 的执行模式由块级控制协议以及 HLS 设计中的子函数结构定义。
- 对于控制驱动的任务级并行（TLP），ap_ctrl_chain 和 ap_ctrl_hs 协议支持顺序执行或流水线执行。对于数据驱动的TLP，ap_ctrl_none是必需的控制协议。
- ap_ctrl_chain 控制协议是 Vitis kernel Flow 的默认协议。
- ap_ctrl_hs 块级控制协议是 Vivado IP Flow 的默认协议。
- 然而，当将 HLS 设计链接在一起时，应使用 ap_ctrl_chain，因为它能更好地支持流水线执行。
- 可以使用 INTERFACE 编译指示或指令在函数返回值（return）上指定块级控制协议。
2）重叠模式
允许在当前事务完成之前开始新事务的执行。通过函数流水线、循环回绕或数据流执行，一旦设计准备就绪，重叠的块运行就可以开始处理额外的数据。
3）顺序模式
要求当前事务完成之后，才能开始新事务的执行。
4）自动重启模式
自动重启模式允许 HLS 设计在准备好开始处理额外数据时自动重启模块。此模式同时支持重叠执行和顺序执行。自动重启是数据驱动的 TLP 设计的方法，但也可以应用于控制驱动的TLP设计。
2.2 接口范式
2.2.1 存储器
描述：内核通过存储器（如 DDR、HBM、PLRAM/BRAM/URAM）来访问数据
接口类型：ap_memory 和 AXI4 AXI4 Memory Mapped (m_axi)
2.2.2 串流
描述：数据从另一个流源（如视频处理器或其他内核）流入内核，也可以从内核流出。
接口类型：ap_fifo, AXI4-Stream (axis)
2.3.3 寄存器
描述：内核通过寄存器接口进行读写操作访问数据。
接口类型：ap_none、ap_hs、ap_ack、ap_ovld、ap_vld、AXI4-Lite adapter (s_axilite)
2.3 Vitis Kernel Flow
2.3.1 默认的协议
| C 语言实参类型 | 范式 | 接口协议 I/O/Inout |
| 标量（值传递） | 寄存器 | AXI4-Lite（s_axilite） |
| 阵列 | 存储器 | AXI4 存储器映射（m_axi） |
| 指向阵列的指针 | 存储器 | AXI4 存储器映射（m_axi） |
| 指向标量的指针 | 寄存器 | AXI4-Lite（s_axilite） |
| 引用 | 寄存器 | AXI4-Lite（s_axilite） |
| hls::stream | 串流 | AXI4-Stream（axis） |
2.3.2 vadd 代码
#include <stdint.h>
#include <hls_stream.h>
const int c_size = 4096;
static void read_input(unsigned int* in, hls::stream<unsigned int>& inStream, int size) {
mem_rd:
for (int i = 0; i < size; i++) {
#pragma HLS LOOP_TRIPCOUNT min = c_size max = c_size
inStream << in[i];
}
}
static void compute_add(hls::stream<unsigned int>& inStream1,
hls::stream<unsigned int>& inStream2,
hls::stream<unsigned int>& outStream,
int size) {
compute:
for (int i = 0; i < size; i++) {
#pragma HLS LOOP_TRIPCOUNT min = c_size max = c_size
outStream << (inStream1.read() + inStream2.read());
}
}
static void write_result(unsigned int* out, hls::stream<unsigned int>& outStream, int size) {
mem_wr:
for (int i = 0; i < size; i++) {
#pragma HLS LOOP_TRIPCOUNT min = c_size max = c_size
out[i] = outStream.read();
}
}
extern "C" {
void vadd(unsigned int* in1, unsigned int* in2, unsigned int* out, int size) {
#pragma HLS INTERFACE m_axi port = in1 bundle = gmem0 depth=c_size
#pragma HLS INTERFACE m_axi port = in2 bundle = gmem1 depth=c_size
#pragma HLS INTERFACE m_axi port = out bundle = gmem0 depth=c_size
static hls::stream<unsigned int> inStream1("input_stream_1");
static hls::stream<unsigned int> inStream2("input_stream_2");
static hls::stream<unsigned int> outStream("output_stream");
#pragma HLS dataflow
read_input(in1, inStream1, size);
read_input(in2, inStream2, size);
compute_add(inStream1, inStream2, outStream, size);
write_result(out, outStream, size);
}
}对应的 config 文件：
part=xck26-sfvc784-2LV-c
[hls]
flow_target=vitis
package.output.format=ip_catalog
package.output.syn=false
syn.file=vadd.cpp
tb.file=test.cpp
syn.top=vadd
cosim.trace_level=allIP 图：
2.3.3 查看报告
================================================================
== Synthesis Summary Report of 'vadd'
================================================================
+ General Information:
* Date: xxxx
* Version: 2024.1 (Build 5069499 on May 21 2024)
* Project: vadd
* Solution: hls (Vitis Kernel Flow Target)
* Product family: zynquplus
* Target device: xck26-sfvc784-2LV-c
+ Performance & Resource Estimates:
PS: '+' for module; 'o' for loop; '*' for dataflow
+----------------------------------+------+------+---------+-----------+----------+---------+------+----------+--------+----+-----------+-----------+-----+
| Modules | Issue| | Latency | Latency | Iteration| | Trip | | | | | | |
| & Loops | Type | Slack| (cycles)| (ns) | Latency | Interval| Count| Pipelined| BRAM | DSP| FF | LUT | URAM|
+----------------------------------+------+------+---------+-----------+----------+---------+------+----------+--------+----+-----------+-----------+-----+
|+ vadd* | -| 0.00| 4243| 4.243e+04| -| 4173| -| dataflow| 6 (2%)| -| 3329 (1%)| 4371 (3%)| -|
| + entry_proc | -| 5.46| 0| 0.000| -| 0| -| no| -| -| 3 (~0%)| 29 (~0%)| -|
| + read_input | -| 0.00| 4172| 4.172e+04| -| 4172| -| no| -| -| 238 (~0%)| 785 (~0%)| -|
| + read_input_Pipeline_mem_rd | -| 0.00| 4099| 4.099e+04| -| 4099| -| no| -| -| 68 (~0%)| 135 (~0%)| -|
| o mem_rd | -| 7.30| 4097| 4.097e+04| 3| 1| 4096| yes| -| -| -| -| -|
| + read_input_1 | -| 0.00| 4170| 4.170e+04| -| 4170| -| no| -| -| 371 (~0%)| 258 (~0%)| -|
| o mem_rd | -| 7.30| 4168| 4.168e+04| 74| 1| 4096| yes| -| -| -| -| -|
| + compute_add | -| 2.61| 4100| 4.100e+04| -| 4100| -| no| -| -| 71 (~0%)| 261 (~0%)| -|
| + compute_add_Pipeline_compute | -| 2.61| 4098| 4.098e+04| -| 4098| -| no| -| -| 34 (~0%)| 185 (~0%)| -|
| o compute | -| 7.30| 4096| 4.096e+04| 2| 1| 4096| yes| -| -| -| -| -|
| + write_result | -| 0.00| 4170| 4.170e+04| -| 4170| -| no| -| -| 267 (~0%)| 786 (~0%)| -|
| + write_result_Pipeline_mem_wr | -| 0.00| 4099| 4.099e+04| -| 4099| -| no| -| -| 68 (~0%)| 137 (~0%)| -|
| o mem_wr | -| 7.30| 4097| 4.097e+04| 3| 1| 4096| yes| -| -| -| -| -|
+----------------------------------+------+------+---------+-----------+----------+---------+------+----------+--------+----+-----------+-----------+-----+
================================================================
== HW Interfaces
================================================================
* M_AXI
+-------------+------------+------------+---------------+---------+--------+----------+-----------+--------------+--------------+-------------+-------------+-------------------+
| Interface | Read/Write | Data Width | Address Width | Latency | Offset | Register | Max Widen | Max Read | Max Write | Num Read | Num Write | Resource Estimate |
| | | (SW->HW) | | | | | Bitwidth | Burst Length | Burst Length | Outstanding | Outstanding | |
+-------------+------------+------------+---------------+---------+--------+----------+-----------+--------------+--------------+-------------+-------------+-------------------+
| m_axi_gmem0 | READ_WRITE | 32 -> 32 | 64 | 64 | slave | 0 | 512 | 16 | 16 | 16 | 16 | BRAM=4 |
| m_axi_gmem1 | READ_ONLY | 32 -> 32 | 64 | 64 | slave | 0 | 512 | 16 | 16 | 16 | 16 | BRAM=2 |
+-------------+------------+------------+---------------+---------+--------+----------+-----------+--------------+--------------+-------------+-------------+-------------------+
* S_AXILITE Interfaces
+---------------+------------+---------------+--------+----------+
| Interface | Data Width | Address Width | Offset | Register |
+---------------+------------+---------------+--------+----------+
| s_axi_control | 32 | 6 | 16 | 0 |
+---------------+------------+---------------+--------+----------+
* S_AXILITE Registers
+---------------+----------+--------+-------+--------+----------------------------------+------------------------------------------------------------------------------------+
| Interface | Register | Offset | Width | Access | Description | Bit Fields |
+---------------+----------+--------+-------+--------+----------------------------------+------------------------------------------------------------------------------------+
| s_axi_control | CTRL | 0x00 | 32 | RW | Control signals | 0=AP_START 1=AP_DONE 2=AP_IDLE 3=AP_READY 4=AP_CONTINUE 7=AUTO_RESTART 9=INTERRUPT |
| s_axi_control | GIER | 0x04 | 32 | RW | Global Interrupt Enable Register | 0=Enable |
| s_axi_control | IP_IER | 0x08 | 32 | RW | IP Interrupt Enable Register | 0=CHAN0_INT_EN 1=CHAN1_INT_EN |
| s_axi_control | IP_ISR | 0x0c | 32 | RW | IP Interrupt Status Register | 0=CHAN0_INT_ST 1=CHAN1_INT_ST |
| s_axi_control | in1_1 | 0x10 | 32 | W | Data signal of in1 | |
| s_axi_control | in1_2 | 0x14 | 32 | W | Data signal of in1 | |
| s_axi_control | in2_1 | 0x1c | 32 | W | Data signal of in2 | |
| s_axi_control | in2_2 | 0x20 | 32 | W | Data signal of in2 | |
| s_axi_control | out_r_1 | 0x28 | 32 | W | Data signal of out_r | |
| s_axi_control | out_r_2 | 0x2c | 32 | W | Data signal of out_r | |
| s_axi_control | size | 0x34 | 32 | W | Data signal of size | |
+---------------+----------+--------+-------+--------+----------------------------------+------------------------------------------------------------------------------------+
* TOP LEVEL CONTROL
+-----------+---------------+-----------+
| Interface | Type | Ports |
+-----------+---------------+-----------+
| ap_clk | clock | ap_clk |
| ap_rst_n | reset | ap_rst_n |
| interrupt | interrupt | interrupt |
| ap_ctrl | ap_ctrl_chain | |
+-----------+---------------+-----------+
================================================================
== SW I/O Information
================================================================
* Top Function Arguments
+----------+-----------+---------------+
| Argument | Direction | Datatype |
+----------+-----------+---------------+
| in1 | inout | unsigned int* |
| in2 | in | unsigned int* |
| out | inout | unsigned int* |
| size | in | int |
+----------+-----------+---------------+
* SW-to-HW Mapping
+----------+---------------+-----------+----------+-----------------------------------+
| Argument | HW Interface | HW Type | HW Usage | HW Info |
+----------+---------------+-----------+----------+-----------------------------------+
| in1 | m_axi_gmem0 | interface | | channel=0 |
| in1 | s_axi_control | register | offset | name=in1_1 offset=0x10 range=32 |
| in1 | s_axi_control | register | offset | name=in1_2 offset=0x14 range=32 |
| in2 | m_axi_gmem1 | interface | | channel=0 |
| in2 | s_axi_control | register | offset | name=in2_1 offset=0x1c range=32 |
| in2 | s_axi_control | register | offset | name=in2_2 offset=0x20 range=32 |
| out | m_axi_gmem0 | interface | | channel=0 |
| out | s_axi_control | register | offset | name=out_r_1 offset=0x28 range=32 |
| out | s_axi_control | register | offset | name=out_r_2 offset=0x2c range=32 |
| size | s_axi_control | register | | name=size offset=0x34 range=32 |
+----------+---------------+-----------+----------+-----------------------------------+
================================================================
== M_AXI Burst Information
================================================================
Note: All burst requests might be further partitioned into multiple requests during RTL generation based on max_read_burst_length or max_write_burst_length settings.
* Inferred Burst Summary
+--------------+-----------+----------+-------+--------+---------------+
| HW Interface | Direction | Length | Width | Loop | Loop Location |
+--------------+-----------+----------+-------+--------+---------------+
| m_axi_gmem0 | read | variable | 32 | mem_rd | vadd.cpp:8:5 |
| m_axi_gmem0 | write | variable | 32 | mem_wr | vadd.cpp:27:5 |
| m_axi_gmem1 | read | variable | 32 | mem_rd | vadd.cpp:8:5 |
+--------------+-----------+----------+-------+--------+---------------+
* All M_AXI Variable Accesses
+-------------------+----------+-----------------+-----------+--------------+----------+--------+---------------+------------+------------------------------------------------+
| HW Interface | Variable | Access Location | Direction | Burst Status | Length | Loop | Loop Location | Resolution | Problem |
+-------------------+----------+-----------------+-----------+--------------+----------+--------+---------------+------------+------------------------------------------------+
| m_axi_gmem0 | out | vadd.cpp:29:9 | write | Widen Fail | | mem_wr | vadd.cpp:27:5 | 214-234 | Sequential access length is not divisible by 2 |
| m_axi_gmem0 | out | vadd.cpp:29:9 | write | Inferred | variable | mem_wr | vadd.cpp:27:5 | | |
| m_axi_gmem0,gmem1 | in | vadd.cpp:10:11 | read | Widen Fail | | mem_rd | vadd.cpp:8:5 | 214-234 | Sequential access length is not divisible by 2 |
| m_axi_gmem0,gmem1 | in | vadd.cpp:10:11 | read | Inferred | variable | mem_rd | vadd.cpp:8:5 | | |
+-------------------+----------+-----------------+-----------+--------------+----------+--------+---------------+------------+------------------------------------------------+
* Resolution URL: docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=XXX-YYY.html (replace XXX-YYY with column value)
================================================================
== Bind Op Report
================================================================
+----------------------------------+-----+--------+------------+--------+----------+---------+
| Name | DSP | Pragma | Variable | Op | Impl | Latency |
+----------------------------------+-----+--------+------------+--------+----------+---------+
| + vadd | 0 | | | | | |
| + read_input | 0 | | | | | |
| icmp_ln8_fu_94_p2 | | | icmp_ln8 | setgt | auto | 0 |
| empty_fu_104_p3 | | | empty | select | auto_sel | 0 |
| + read_input_Pipeline_mem_rd | 0 | | | | | |
| icmp_ln8_fu_98_p2 | | | icmp_ln8 | setlt | auto | 0 |
| add_ln8_fu_104_p2 | | | add_ln8 | add | fabric | 0 |
| + read_input_1 | 0 | | | | | |
| icmp_ln8_fu_112_p2 | | | icmp_ln8 | setgt | auto | 0 |
| empty_fu_122_p3 | | | empty | select | auto_sel | 0 |
| icmp_ln8_1_fu_146_p2 | | | icmp_ln8_1 | setlt | auto | 0 |
| add_ln8_fu_152_p2 | | | add_ln8 | add | fabric | 0 |
| + compute_add | 0 | | | | | |
| + compute_add_Pipeline_compute | 0 | | | | | |
| icmp_ln19_fu_81_p2 | | | icmp_ln19 | setlt | auto | 0 |
| add_ln19_fu_87_p2 | | | add_ln19 | add | fabric | 0 |
| add_ln21_fu_98_p2 | | | add_ln21 | add | fabric | 0 |
| + write_result | 0 | | | | | |
| icmp_ln27_fu_85_p2 | | | icmp_ln27 | setgt | auto | 0 |
| empty_fu_105_p3 | | | empty | select | auto_sel | 0 |
| + write_result_Pipeline_mem_wr | 0 | | | | | |
| icmp_ln27_fu_102_p2 | | | icmp_ln27 | setlt | auto | 0 |
| add_ln27_fu_108_p2 | | | add_ln27 | add | fabric | 0 |
+----------------------------------+-----+--------+------------+--------+----------+---------+
================================================================
== Storage Report
================================================================
+-------------------+--------------+-------------+------+------+--------+-----------+------+---------+------------------+
| Name | Usage | Type | BRAM | URAM | Pragma | Variable | Impl | Latency | Bitwidth, Depth, |
| | | | | | | | | | Banks |
+-------------------+--------------+-------------+------+------+--------+-----------+------+---------+------------------+
| + vadd | | | 6 | 0 | | | | | |
| control_s_axi_U | interface | s_axilite | | | | | | | |
| gmem0_m_axi_U | interface | m_axi | 4 | | | | | | |
| gmem1_m_axi_U | interface | m_axi | 2 | | | | | | |
| out_r_c_U | fifo channel | scalar prop | | | | out_r_c | srl | 0 | 64, 4, 1 |
| size_c1_U | fifo channel | scalar prop | | | | size_c1 | srl | 0 | 32, 2, 1 |
| inStream1_U | fifo channel | stream | | | | inStream1 | srl | 0 | 32, 2, 1 |
| inStream2_U | fifo channel | stream | | | | inStream2 | srl | 0 | 32, 2, 1 |
| size_c_U | fifo channel | scalar prop | | | | size_c | srl | 0 | 32, 2, 1 |
| outStream_U | fifo channel | stream | | | | outStream | srl | 0 | 32, 2, 1 |
+-------------------+--------------+-------------+------+------+--------+-----------+------+---------+------------------+
================================================================
== Pragma Report
================================================================
* Valid Pragma Syntax
+----------------+----------------------------------------------+-----------------------------+
| Type | Options | Location |
+----------------+----------------------------------------------+-----------------------------+
| loop_tripcount | min = c_size max = c_size | vadd.cpp:9 in read_input |
| loop_tripcount | min = c_size max = c_size | vadd.cpp:20 in compute_add |
| loop_tripcount | min = c_size max = c_size | vadd.cpp:28 in write_result |
| interface | m_axi port = in1 bundle = gmem0 depth=c_size | vadd.cpp:35 in vadd |
| interface | m_axi port = in2 bundle = gmem1 depth=c_size | vadd.cpp:36 in vadd |
| interface | m_axi port = out bundle = gmem0 depth=c_size | vadd.cpp:37 in vadd |
| dataflow | | vadd.cpp:43 in vadd |
+----------------+----------------------------------------------+-----------------------------+2.4 Vivado IP Flow
2.4.1 默认的协议
| C 语言实参类型 | 支持的范式 | 默认范式 | 接口协议 | ||
| In | Out | InOut | |||
| 标量（值传递） | 寄存器 | 寄存器 | ap_none | - | - |
| 阵列 | 存储器、串流 | 存储器 | ap_memory | ap_memory | ap_memory |
| 指针 | 存储器、串流、寄存器 | 寄存器 | ap_none | ap_vld | ap_ovld |
| 引用 | 寄存器 | 寄存器 | ap_none | ap_vld | ap_vld |
| hls::stream | 串流 | 串流 | ap_fifo | ap_fifo | - |
2.4.2 vadd 代码
#include <stdint.h>
#include <hls_stream.h>
const int c_size = 4096;
static void read_input(unsigned int* in, hls::stream<unsigned int>& inStream, int size) {
#pragma HLS INTERFACE mode=ap_ctrl_chain port=return
mem_rd:
for (int i = 0; i < size; i++) {
#pragma HLS LOOP_TRIPCOUNT min = c_size max = c_size
inStream << in[i];
}
}
static void compute_add(hls::stream<unsigned int>& inStream1,
hls::stream<unsigned int>& inStream2,
hls::stream<unsigned int>& outStream,
int size) {
#pragma HLS INTERFACE mode=ap_ctrl_chain port=return
compute:
for (int i = 0; i < size; i++) {
#pragma HLS LOOP_TRIPCOUNT min = c_size max = c_size
outStream << (inStream1.read() + inStream2.read());
}
}
static void write_result(unsigned int* out, hls::stream<unsigned int>& outStream, int size) {
#pragma HLS INTERFACE mode=ap_ctrl_chain port=return
mem_wr:
for (int i = 0; i < size; i++) {
#pragma HLS LOOP_TRIPCOUNT min = c_size max = c_size
out[i] = outStream.read();
}
}
extern "C" {
void vadd(unsigned int* in1, unsigned int* in2, unsigned int* out, int size) {
//#pragma HLS INTERFACE mode=ap_ctrl_chain port=return
//#pragma HLS INTERFACE mode=s_axilite port=return bundle=control
//#pragma HLS INTERFACE mode=s_axilite port=in1 bundle=control
//#pragma HLS INTERFACE mode=s_axilite port=in2 bundle=control
//#pragma HLS INTERFACE mode=s_axilite port=out bundle=control
//#pragma HLS INTERFACE mode=s_axilite port=size bundle=control
#pragma HLS INTERFACE mode=m_axi port=in1 bundle=gmem0 depth=c_size
#pragma HLS INTERFACE mode=m_axi port=in2 bundle=gmem1 depth=c_size
#pragma HLS INTERFACE mode=m_axi port=out bundle=gmem0 depth=c_size
static hls::stream<unsigned int> inStream1("input_stream_1");
static hls::stream<unsigned int> inStream2("input_stream_2");
static hls::stream<unsigned int> outStream("output_stream");
#pragma HLS dataflow
read_input(in1, inStream1, size);
read_input(in2, inStream2, size);
compute_add(inStream1, inStream2, outStream, size);
write_result(out, outStream, size);
}
}对应的 config 文件：
part=xck26-sfvc784-2LV-c
[hls]
flow_target=vivado
package.output.format=ip_catalog
package.output.syn=false
syn.file=vadd.cpp
syn.top=vaddIP 图：
2.4.3 查看报告
================================================================
== Synthesis Summary Report of 'vadd'
================================================================
+ General Information:
* Date: xxxx
* Version: 2024.1 (Build 5069499 on May 21 2024)
* Project: vadd
* Solution: hls (Vivado IP Flow Target)
* Product family: zynquplus
* Target device: xck26-sfvc784-2LV-c
+ Performance & Resource Estimates:
PS: '+' for module; 'o' for loop; '*' for dataflow
+----------------------------------+------+------+---------+-----------+----------+---------+------+----------+--------+----+-----------+-----------+-----+
| Modules | Issue| | Latency | Latency | Iteration| | Trip | | | | | | |
| & Loops | Type | Slack| (cycles)| (ns) | Latency | Interval| Count| Pipelined| BRAM | DSP| FF | LUT | URAM|
+----------------------------------+------+------+---------+-----------+----------+---------+------+----------+--------+----+-----------+-----------+-----+
|+ vadd* | -| 0.00| 4117| 4.117e+04| -| 4110| -| dataflow| 6 (2%)| -| 3030 (1%)| 3648 (3%)| -|
| + entry_proc | -| 5.46| 0| 0.000| -| 0| -| no| -| -| 3 (~0%)| 29 (~0%)| -|
| + read_input | -| 0.00| 4109| 4.109e+04| -| 4109| -| no| -| -| 175 (~0%)| 449 (~0%)| -|
| + read_input_Pipeline_mem_rd | -| 0.00| 4099| 4.099e+04| -| 4099| -| no| -| -| 68 (~0%)| 135 (~0%)| -|
| o mem_rd | -| 7.30| 4097| 4.097e+04| 3| 1| 4096| yes| -| -| -| -| -|
| + read_input_1 | -| 0.00| 4107| 4.107e+04| -| 4107| -| no| -| -| 245 (~0%)| 258 (~0%)| -|
| o mem_rd | -| 7.30| 4105| 4.105e+04| 11| 1| 4096| yes| -| -| -| -| -|
| + compute_add | -| 2.61| 4100| 4.100e+04| -| 4100| -| no| -| -| 71 (~0%)| 261 (~0%)| -|
| + compute_add_Pipeline_compute | -| 2.61| 4098| 4.098e+04| -| 4098| -| no| -| -| 34 (~0%)| 185 (~0%)| -|
| o compute | -| 7.30| 4096| 4.096e+04| 2| 1| 4096| yes| -| -| -| -| -|
| + write_result | -| 0.00| 4107| 4.107e+04| -| 4107| -| no| -| -| 204 (~0%)| 463 (~0%)| -|
| + write_result_Pipeline_mem_wr | -| 0.00| 4099| 4.099e+04| -| 4099| -| no| -| -| 68 (~0%)| 137 (~0%)| -|
| o mem_wr | -| 7.30| 4097| 4.097e+04| 3| 1| 4096| yes| -| -| -| -| -|
+----------------------------------+------+------+---------+-----------+----------+---------+------+----------+--------+----+-----------+-----------+-----+
================================================================
== HW Interfaces
================================================================
* M_AXI
+-------------+------------+------------+---------------+---------+--------+----------+-----------+--------------+--------------+-------------+-------------+-------------------+
| Interface | Read/Write | Data Width | Address Width | Latency | Offset | Register | Max Widen | Max Read | Max Write | Num Read | Num Write | Resource Estimate |
| | | (SW->HW) | | | | | Bitwidth | Burst Length | Burst Length | Outstanding | Outstanding | |
+-------------+------------+------------+---------------+---------+--------+----------+-----------+--------------+--------------+-------------+-------------+-------------------+
| m_axi_gmem0 | READ_WRITE | 32 -> 32 | 64 | 0 | slave | 0 | 0 | 16 | 16 | 16 | 16 | BRAM=4 |
| m_axi_gmem1 | READ_ONLY | 32 -> 32 | 64 | 0 | slave | 0 | 0 | 16 | 16 | 16 | 16 | BRAM=2 |
+-------------+------------+------------+---------------+---------+--------+----------+-----------+--------------+--------------+-------------+-------------+-------------------+
* S_AXILITE Interfaces
+---------------+------------+---------------+--------+----------+
| Interface | Data Width | Address Width | Offset | Register |
+---------------+------------+---------------+--------+----------+
| s_axi_control | 32 | 6 | 16 | 0 |
+---------------+------------+---------------+--------+----------+
* S_AXILITE Registers
+---------------+----------+--------+-------+--------+----------------------+
| Interface | Register | Offset | Width | Access | Description |
+---------------+----------+--------+-------+--------+----------------------+
| s_axi_control | in1_1 | 0x10 | 32 | W | Data signal of in1 |
| s_axi_control | in1_2 | 0x14 | 32 | W | Data signal of in1 |
| s_axi_control | in2_1 | 0x1c | 32 | W | Data signal of in2 |
| s_axi_control | in2_2 | 0x20 | 32 | W | Data signal of in2 |
| s_axi_control | out_r_1 | 0x28 | 32 | W | Data signal of out_r |
| s_axi_control | out_r_2 | 0x2c | 32 | W | Data signal of out_r |
+---------------+----------+--------+-------+--------+----------------------+
* Other Ports
+------+---------+-----------+----------+
| Port | Mode | Direction | Bitwidth |
+------+---------+-----------+----------+
| size | ap_none | in | 32 |
+------+---------+-----------+----------+
* TOP LEVEL CONTROL
+-----------+------------+-----------------------------------+
| Interface | Type | Ports |
+-----------+------------+-----------------------------------+
| ap_clk | clock | ap_clk |
| ap_rst_n | reset | ap_rst_n |
| ap_ctrl | ap_ctrl_hs | ap_done ap_idle ap_ready ap_start |
+-----------+------------+-----------------------------------+
================================================================
== SW I/O Information
================================================================
* Top Function Arguments
+----------+-----------+---------------+
| Argument | Direction | Datatype |
+----------+-----------+---------------+
| in1 | inout | unsigned int* |
| in2 | in | unsigned int* |
| out | inout | unsigned int* |
| size | in | int |
+----------+-----------+---------------+
* SW-to-HW Mapping
+----------+---------------+-----------+----------+-----------------------------------+
| Argument | HW Interface | HW Type | HW Usage | HW Info |
+----------+---------------+-----------+----------+-----------------------------------+
| in1 | m_axi_gmem0 | interface | | channel=0 |
| in1 | s_axi_control | register | offset | name=in1_1 offset=0x10 range=32 |
| in1 | s_axi_control | register | offset | name=in1_2 offset=0x14 range=32 |
| in2 | m_axi_gmem1 | interface | | channel=0 |
| in2 | s_axi_control | register | offset | name=in2_1 offset=0x1c range=32 |
| in2 | s_axi_control | register | offset | name=in2_2 offset=0x20 range=32 |
| out | m_axi_gmem0 | interface | | channel=0 |
| out | s_axi_control | register | offset | name=out_r_1 offset=0x28 range=32 |
| out | s_axi_control | register | offset | name=out_r_2 offset=0x2c range=32 |
| size | size | port | | |
+----------+---------------+-----------+----------+-----------------------------------+
================================================================
== M_AXI Burst Information
================================================================
Note: All burst requests might be further partitioned into multiple requests during RTL generation based on max_read_burst_length or max_write_burst_length settings.
* Inferred Burst Summary
+--------------+-----------+----------+-------+--------+---------------+
| HW Interface | Direction | Length | Width | Loop | Loop Location |
+--------------+-----------+----------+-------+--------+---------------+
| m_axi_gmem0 | read | variable | 32 | mem_rd | vadd.cpp:10:5 |
| m_axi_gmem0 | write | variable | 32 | mem_wr | vadd.cpp:33:5 |
| m_axi_gmem1 | read | variable | 32 | mem_rd | vadd.cpp:10:5 |
+--------------+-----------+----------+-------+--------+---------------+
* All M_AXI Variable Accesses
+-------------------+----------+-----------------+-----------+--------------+----------+--------+---------------+------------+-------------------------------------------------------------------------------------------------------+
| HW Interface | Variable | Access Location | Direction | Burst Status | Length | Loop | Loop Location | Resolution | Problem |
+-------------------+----------+-----------------+-----------+--------------+----------+--------+---------------+------------+-------------------------------------------------------------------------------------------------------+
| m_axi_gmem0 | out | vadd.cpp:35:9 | write | Widen Fail | | mem_wr | vadd.cpp:33:5 | 214-353 | Could not widen since type i32 size is greater than or equal to the max_widen_bitwidth threshold of 0 |
| m_axi_gmem0 | out | vadd.cpp:35:9 | write | Inferred | variable | mem_wr | vadd.cpp:33:5 | | |
| m_axi_gmem0,gmem1 | in | vadd.cpp:12:11 | read | Widen Fail | | mem_rd | vadd.cpp:10:5 | 214-353 | Could not widen since type i32 size is greater than or equal to the max_widen_bitwidth threshold of 0 |
| m_axi_gmem0,gmem1 | in | vadd.cpp:12:11 | read | Inferred | variable | mem_rd | vadd.cpp:10:5 | | |
+-------------------+----------+-----------------+-----------+--------------+----------+--------+---------------+------------+-------------------------------------------------------------------------------------------------------+
* Resolution URL: docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=XXX-YYY.html (replace XXX-YYY with column value)
================================================================
== Bind Op Report
================================================================
+----------------------------------+-----+--------+-------------+--------+----------+---------+
| Name | DSP | Pragma | Variable | Op | Impl | Latency |
+----------------------------------+-----+--------+-------------+--------+----------+---------+
| + vadd | 0 | | | | | |
| + read_input | 0 | | | | | |
| icmp_ln10_fu_94_p2 | | | icmp_ln10 | setgt | auto | 0 |
| empty_fu_104_p3 | | | empty | select | auto_sel | 0 |
| + read_input_Pipeline_mem_rd | 0 | | | | | |
| icmp_ln10_fu_96_p2 | | | icmp_ln10 | setlt | auto | 0 |
| add_ln10_fu_102_p2 | | | add_ln10 | add | fabric | 0 |
| + read_input_1 | 0 | | | | | |
| icmp_ln10_fu_112_p2 | | | icmp_ln10 | setgt | auto | 0 |
| empty_fu_122_p3 | | | empty | select | auto_sel | 0 |
| icmp_ln10_1_fu_146_p2 | | | icmp_ln10_1 | setlt | auto | 0 |
| add_ln10_fu_152_p2 | | | add_ln10 | add | fabric | 0 |
| + compute_add | 0 | | | | | |
| + compute_add_Pipeline_compute | 0 | | | | | |
| icmp_ln23_fu_81_p2 | | | icmp_ln23 | setlt | auto | 0 |
| add_ln23_fu_87_p2 | | | add_ln23 | add | fabric | 0 |
| add_ln25_fu_98_p2 | | | add_ln25 | add | fabric | 0 |
| + write_result | 0 | | | | | |
| icmp_ln33_fu_85_p2 | | | icmp_ln33 | setgt | auto | 0 |
| empty_fu_105_p3 | | | empty | select | auto_sel | 0 |
| + write_result_Pipeline_mem_wr | 0 | | | | | |
| icmp_ln33_fu_100_p2 | | | icmp_ln33 | setlt | auto | 0 |
| add_ln33_fu_106_p2 | | | add_ln33 | add | fabric | 0 |
+----------------------------------+-----+--------+-------------+--------+----------+---------+
================================================================
== Storage Report
================================================================
+-------------------+--------------+-------------+------+------+--------+-----------+------+---------+------------------+
| Name | Usage | Type | BRAM | URAM | Pragma | Variable | Impl | Latency | Bitwidth, Depth, |
| | | | | | | | | | Banks |
+-------------------+--------------+-------------+------+------+--------+-----------+------+---------+------------------+
| + vadd | | | 6 | 0 | | | | | |
| control_s_axi_U | interface | s_axilite | | | | | | | |
| gmem0_m_axi_U | interface | m_axi | 4 | | | | | | |
| gmem1_m_axi_U | interface | m_axi | 2 | | | | | | |
| out_r_c_U | fifo channel | scalar prop | | | | out_r_c | srl | 0 | 64, 4, 1 |
| size_c1_U | fifo channel | scalar prop | | | | size_c1 | srl | 0 | 32, 2, 1 |
| inStream1_U | fifo channel | stream | | | | inStream1 | srl | 0 | 32, 2, 1 |
| inStream2_U | fifo channel | stream | | | | inStream2 | srl | 0 | 32, 2, 1 |
| size_c_U | fifo channel | scalar prop | | | | size_c | srl | 0 | 32, 2, 1 |
| outStream_U | fifo channel | stream | | | | outStream | srl | 0 | 32, 2, 1 |
+-------------------+--------------+-------------+------+------+--------+-----------+------+---------+------------------+
================================================================
== Pragma Report
================================================================
* Valid Pragma Syntax
+----------------+-----------------------------------------------+-------------------------------------+
| Type | Options | Location |
+----------------+-----------------------------------------------+-------------------------------------+
| interface | mode=ap_ctrl_chain port=return | vadd.cpp:7 in read_input, return |
| loop_tripcount | min = c_size max = c_size | vadd.cpp:11 in read_input |
| interface | mode=ap_ctrl_chain port=return | vadd.cpp:20 in compute_add, return |
| loop_tripcount | min = c_size max = c_size | vadd.cpp:24 in compute_add |
| interface | mode=ap_ctrl_chain port=return | vadd.cpp:30 in write_result, return |
| loop_tripcount | min = c_size max = c_size | vadd.cpp:34 in write_result |
| interface | mode=m_axi port=in1 bundle=gmem0 depth=c_size | vadd.cpp:41 in vadd, in1 |
| interface | mode=m_axi port=in2 bundle=gmem1 depth=c_size | vadd.cpp:42 in vadd, in2 |
| interface | mode=m_axi port=out bundle=gmem0 depth=c_size | vadd.cpp:43 in vadd, out |
| dataflow | | vadd.cpp:49 in vadd |
+----------------+-----------------------------------------------+-------------------------------------+3. 测试与波形
3.1 TestBench
#include <iostream>
#include <cstdlib>
#include <cstring>
const int TEST_SIZE = 8;
extern "C" void vadd(unsigned int* in1, unsigned int* in2, unsigned int* out, int size);
int main() {
unsigned int* in1 = new unsigned int[TEST_SIZE];
unsigned int* in2 = new unsigned int[TEST_SIZE];
unsigned int* out = new unsigned int[TEST_SIZE];
unsigned int* expected = new unsigned int[TEST_SIZE];
// 生成测试输入数据
for (int i = 0; i < TEST_SIZE; i++) {
in1[i] = i;
in2[i] = TEST_SIZE - i;
expected[i] = in1[i] + in2[i]; // 计算期望结果
}
// 调用 vadd 计算
vadd(in1, in2, out, TEST_SIZE);
vadd(in1, in2, out, TEST_SIZE);
vadd(in1, in2, out, TEST_SIZE);
vadd(in1, in2, out, TEST_SIZE);
// 验证计算结果
bool pass = true;
for (int i = 0; i < TEST_SIZE; i++) {
if (out[i] != expected[i]) {
std::cerr << "Test failed at index " << i
<< ": expected " << expected[i] << ", got " << out[i] << std::endl;
pass = false;
break; // 发现错误后立即停止
}
}
if (pass) {
std::cout << "Test passed successfully!" << std::endl;
}
// 释放内存
delete[] in1;
delete[] in2;
delete[] out;
delete[] expected;
return pass ? 0 : 1;
}
3.2 理解控制协议
3.3 Wave Viewer
3.3.1 整体波形
通过 Wave Viewer，观察三个模块之间的块级协议是如何工作的。
3.3.2 ap_ctrl 信号
比如，ap_start ap_done ap_continue 等信号的变化。
4. 模块拆分
4.1 分析
如果将 read_input、compute_add、write_result 将失去顶层协议。
与 mm2s、s2mm 情况类似。
4.2 compute_add
#include <stdint.h>
#include <hls_stream.h>
const int c_size = 4096;
extern "C" {
void example(hls::stream<unsigned int>& inStream1,
hls::stream<unsigned int>& inStream2,
hls::stream<unsigned int>& outStream,
int size) {
#pragma HLS INTERFACE mode=ap_ctrl_chain port=return
compute:
for (int i = 0; i < size; i++) {
#pragma HLS LOOP_TRIPCOUNT min = c_size max = c_size
outStream << (inStream1.read() + inStream2.read());
}
}
}config file：
part=xck26-sfvc784-2LV-c
[hls]
flow_target=vivado
package.output.format=ip_catalog
package.output.syn=false
syn.file=compute_vadd.cpp
syn.top=example4.2 IP 图
注意：需要修改 IP 中 stream port 的 Master/Slave 属性。
5. 总结
- 区分 axis 与 ap_fifo
- #pragma HLS interface axis port=s
