module VGA_CTRL(
    Clk,
    Reset_n,
    Data,
    Data_Req,
    VGA_HS, //行
    VGA_VS, //场
    VGA_BLK, //数据有效的那一段
    VGA_RGB
);
    
    input Clk;
    input Reset_n;
    input [23:0]Data;
    output reg Data_Req;
    output reg VGA_HS;
    output reg VGA_VS; 
    output reg VGA_BLK;
    output reg [23:0]VGA_RGB;//{R[7:0]、G[7:0]、B[7:0]}
    
    localparam Hsync_End = 800;
    localparam HS_End = 96;
    localparam Vsync_End = 525;
    localparam VS_End = 2;
    localparam Hdat_Begin = 144;
    localparam Hdat_End = 784;
    localparam Vdat_Begin =  35;
    localparam Vdat_End = 515;
    
    reg [9:0]hcnt;
    always@(posedge Clk or negedge Reset_n)
    if(!Reset_n)
        hcnt <= 0;
    else if(hcnt >= Hsync_End -1)
        hcnt <= 0;
    else
        hcnt <= hcnt + 1'b1;
        
//    assign VGA_HS = (hcnt < HS_End - 1'd1)?0:1;
 // 改成时序逻辑后时间节点会出现后移，需要解决
    always@(posedge Clk)
        VGA_HS <= (hcnt < HS_End)?0:1;
    
    reg [9:0]vcnt;
    always@(posedge Clk or negedge Reset_n)
    if(!Reset_n)
        vcnt <= 0;
    else if(hcnt == Hsync_End -1)begin
        if(vcnt >= Vsync_End -1)
            vcnt <= 0;
        else
            vcnt <= vcnt + 1'd1;
    end
    else
        vcnt <= vcnt;
    
//    assign VGA_VS = (vcnt < VS_End - 1'd1)?0:1;
    always@(posedge Clk)
        VGA_VS  <= (vcnt < VS_End)?0:1;
        
    //BLK表示的就是输出输出的时间段
//    assign VGA_BLK = ((hcnt >= Hdat_Begin - 1) && (hcnt < Hdat_End - 1) && (vcnt >= Vdat_Begin - 1) && (vcnt < Vdat_End))?1:0;
//    always@(posedge Clk)
//         VGA_BLK <= ((hcnt >= Hdat_Begin - 1) && (hcnt < Hdat_End - 1) && (vcnt >= Vdat_Begin - 1) && (vcnt < Vdat_End))?1:0;   

    always@(posedge Clk)
       Data_Req <= ((hcnt >= Hdat_Begin - 1) && (hcnt < Hdat_End - 1) && (vcnt >= Vdat_Begin) && (vcnt < Vdat_End))?1:0;
    
    always@(posedge Clk)
       VGA_BLK <= Data_Req;     
            
//    assign VGA_RGB = VGA_BLK? Data:0;
    always@(posedge Clk)
        VGA_RGB <= Data_Req? Data:0;
        
    
        
endmodule