Meint Smit et al 2014 Semicond. Sci. Technol. 29 083001

9.通用测试

9.1. 晶圆验证

在通用工艺中，必须对每批次晶片的工艺性能进行验证；客户将期待这样的验证。在MPW中，验证用户ASPIC工艺性能是不实际的；每个ASPIC都需要不同的测试设置和程序，ASPIC的失败并不意味着工艺失败，问题也可能出现在用户设计中。验证通用过程的唯一实用方法是包括用于BBB表征的测试单元。如果BBB的性能是可以的，那么基于这些BBB的所有元件的性能也应该是可以的——如果它们设计得当，并且流程足够成熟。通过将测试限制在BBB上，我们避免了最终出现大量构建块，而这些构建块的测试将需要不切实际的大测试单元。此外，对于工艺技术开发来说，聚焦在一小组BBB是可行的，工艺优化可以集中在这些BBB上。

9.2. 晶圆上测试

测试光学元件比测试电气元件更困难。首先，光端口只有在晶片被切割后才可接近，其次，光在波导中或波导外的精确耦合的对准公差要求很高，因此测试很慢。电测量的对准公差容限更大，因为只要接触良好，电气触点就可更大，一些未对准的影响就很小。电测量的一大优点是可以在晶圆上进行：不需要对晶圆进行切片测试，这使得自动化测试更加容易。

因此，我们正在研究对光子IC中最重要的构建块的光学特性进行晶圆上测试的可能性。在PARADIGM项目中，我们正在研究两种方法：一种是在芯片中集成垂直输出耦合器，垂直光学探针可以访问该耦合器。另一种方法是将待测器件（DUT）与源和检测器集成在一起。在后一种方法中，我们将测试光路（即使是复杂的测试光路）添加到ASPIC设计中，这相对简单。我们将在本节中简要介绍这种方法。

测量传输损耗的一般方法是将其与参考器件（通常是直波导部分）的传输进行比较。如图28所示，我们在源和探测器之间集成DUT和参考器件，在假设源相同的情况下，通过比较检测器的输出电流来测量，从而在晶圆上实现这一点。作为一个源，我们可以使用集成的SOA部分，它将生成一个宽的频谱，以便在整个频带上对测量的传输进行平均（加权）。如果我们使用集成DBR激光器作为光源，我们可以在特定波长下进行测量。该方法的准确性取决于集成测试源和检测器的重复一致性。

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Oclaro和COBRA通用集成过程中最重要的BBB是无源波导器件、SOA和相位调制器。它们最重要的特性分别是传输损耗、增益谱和电光效率。为了说明我们的方法，我们将讨论我们目前正在研究的三种结构，以用电探针测量它们。

波导损耗原则上可以通过比较短波导段和长波导段的传输来测量。如果传输损耗较低，则需要长波导段来足够准确地测量损耗，并且测试结构将具有较大的占地面积。另一种方法如图29所示，这基于这样一个原理，即环形谐振器的传输对环中的损耗非常敏感。为了测试波导损耗，我们在带监测二极管的可调谐DBR激光器和检测二极管之间插入一个由MMI耦合器形成的环。通过扫描波长并将检测器电流标准化为监测二极管的电流，我们记录了如图右侧所示的曲线。通过测量最大和最小功率之间的消光比，我们可以确定波导损耗。为了进一步提高测量精度，我们可以比较具有相同曲线但不同直波导段长度的环。

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SOA增益。图30展示了用于测量光放大器增益谱的测试结构。如果SOA1和SOA2相同，则SOA2开启和关闭时SOA1的输出功率之比就是SOA1的增益。以这种方式测量的增益是增益谱上的加权平均值。如果我们在SOA1后面插入AWG，并将光电探测器连接到每个输出端口，我们可以测量AWG的每个波长通道的光谱增益。这将为我们提供如图30中红点所示的采样增益频谱。几个通道就足以充分验证SOA性能。

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电光效率。测量Vπ（相位调制器引入180°相移的电压）的一种简单方法是将其插入源和检测器之间的MZI中，如图31所示，将传输记录为电压的函数。Vπ是两个极小值之间的电压差。通常情况下，它与电压有关，因此需要更复杂的方法来找到ϕ–V曲线。

这三个例子说明了如何使用电探针在晶片上测量光电特性。在图5中，以插图形式出现的放大MPW单元显示了包含如上所述的多个测试结构的测试单元。通过测量BBB的性能并将其与标准进行比较，这种测试单元可用于快速准确地验证晶片。

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10.未来前景

由于在开发基于InP的单片集成和硅光子学的晶圆技术基础设施方面进行了大量投资（在欧洲和国家项目中远远超过5000万欧元），欧洲在建立这种新的工作方式方面取得了重大进展。

10.1. 技术发展

如本文所述，自2007年以来，COBRA已经提供了对第一代（G1）InP研究平台的小规模访问。工艺能力正在逐步提高，目前ASPIC集成了10 Gb /s速度的激光器、光放大器、调制器和检测器以及各种无源光学元件。该平台适用于研究和原型设计，但不适用于批量生产。2009年，EuroPIC项目开始将晶圆模型从大学环境转移到工业和半工业平台（Oclaro和FhG-HHI的晶圆厂），并开始开发软件设计套件和标准化封装解决方案。EuroPIC平台技术的能力列于表2的2012栏。本文第6节介绍了本项目中开发的一些ASPIC。结果非常有希望，JePPIX平台[44]已经开始对这些晶圆工艺进行半商业化访问。预计在2015/16年度向全面商业运营过渡，前提是当时的市场需求证明了这种过渡是合理的。

2010年，PARADIGM项目开始开发第二代（G2）平台，该平台具有改进的功能和性能：能够提供高达40 Gb /s的发射机和接收机功能，提供卓越的激光器和放大器，更宽泛的发射和检测波长以及其他先进功能。该工艺将与先进的特定应用技术相竞争，但入门成本要低得多。表2第2015列列出了其目标属性。此外，该项目设想开发低成本的通用包和具有强大元件库的复杂PDK，如第7和第8节所述。在项目期间，为选定的外部用户提供小规模访问。假设有一个可行的商业案例，预计在2017年左右全面商业运营，并提前进入研发阶段。

一个重要的发展是电和光的单片集成。在硅光子学中，几个小组已经证明了光路在硅衬底上的硅膜中的集成，其中一些还包括激光器等有源光学元件。硅光子学光路中激光器集成的主流是通过在光子硅层顶部结合基于InP的III–V层堆叠，并处理III–V中的激光器和硅层中的其他元件[92–94]。在这种方法中，最终需要三层：

（1） 一个CMOS电子层

（2） 一个硅光子层

（3） 一个InP光子层

两个光子层之间的有效耦合是困难的，并且需要在芯片上具有显著大的区域，尤其是在有源元件变得更小的情况下。COBRA采用了一种方法，将全光子功能集成在单个基于InP的硅上膜（IMOS）中，从而通过消除硅光子层和两个光子层之间的耦合问题将层数减少到两个[95]。该技术可以在CMOS晶圆厂（具有专用工艺线）中实现，也可以在InP晶圆厂中实现。它可能成为将InP光子学与硅电子技术相结合的第三代（G3）晶圆技术。

10.2. 成本发展

人们普遍认为，InP PICs比硅光子PICs贵得多。通过应用通用晶圆模型，InP PIC的研发和原型制作成本可以降低一个数量级以上，这使得InP PIC与硅光子非常有竞争力。目前，JePPIX（www.JePPIX.eu）为基于InP的晶圆工艺提供MPW运行的半商业访问，ePIXfab（www.ePIXfab.eu）和OpSIS（www.opsisfoundry.org）为硅光子提供半商业访问。为了进行比较，所提供的功能和性能以及每平方毫米设计面积的成本是最相关的数字。交付的芯片数量也可能是相关的，但通常在第一阶段，测试新设计只需要几个芯片。如果我们将最先进的硅光子工艺与最先进的基于InP的工艺进行比较，我们会发现在MPW运行中，InP以更低的成本提供了更多的功能（激光器、光放大器和更好的调制器），无论MPW的价格还是平方毫米的价格。

对于这两种技术，小规模生产和原型设计的成本将由非共享成本主导，无论是晶圆工艺、PDK和IPB、模型开发、表征、软件开发，还是最终用户特定的芯片设计时间和资源。在这里，InP似乎具有优势，因为大规模CMOS晶圆厂的研发成本明显高于小型InP晶圆厂，这使得通用InP技术的入门成本低于硅光子学技术。对于批量生产，InP晶圆的每平方毫米成本肯定高于硅光子学，这主要是由于使用的衬底晶圆较小，生产量较小。目前，它们在10-20€/mm2的范围内，但一旦晶圆厂获得更高的订单，这一成本就会减少。由于硅光子学需要更高的研发投资，InP在小批量甚至中批量生产方面可能具有竞争优势。

为了与硅光子学进行公平的比较，我们还必须在比较中包括封装成本。在目前的光子封装技术中，封装成本明显高于芯片成本，因此对于最终产品来说，芯片的价格不如集成在芯片中的功能重要。由于InP还集成了大多数应用中所需的激光器和光放大器，因此封装成本将低于硅光子芯片，在硅光子芯片中，激光器必须以更昂贵的混合方式集成。因此，我们预计，尽管封装的InP PICs的平方毫米价格更高，但与封装的硅光子PICs相比，它将极具竞争力。

10.3. 应用

预计研发时间和芯片制造成本的大幅减少将导致PIC在光子元件市场的份额大幅增长。到目前为止，PICs的商业部署主要局限于电信核心网络应用的特定领域，在这些领域，它们的功能无法与竞争技术相匹配。电信是光子技术开发的一个相对小众的领域，约占全球光子市场的5%[96]。尽管如此，电信业的严格要求正在推动PIC研究。因此，在其他已建立的光子市场中利用PIC技术的机会是巨大的，如光纤传感器解调 单元、医疗诊断、计量以及当今光子学无法提供有竞争力的价格水平的许多应用。在第6节中，讨论了在这些市场中应用的一些ASPIC。

通用晶圆方法的另一个重要优势是上市时间短。因为ASPIC是在合格的晶圆工艺中开发的，所以升级到更大的生产量是直接的：一旦ASPIC设计满足用户要求，用户就可以在开发ASPIC的同一工艺中订购许多晶圆，现在他可以完全用自己的设计来填充这些晶圆。对于设计面积为4×5 mm2的ASPIC，单个3’晶片将包含100多个芯片。因此，用1000个晶片可以获得10万个芯片的体积，这可以由中型InP晶圆厂轻松处理。

图32显示了2012年JePPIX路线图[97]中发布的基于InP的ASPICS实现的市场发展预测。它是基于MPW运行中开发的ASPIC数量的预期增长。在图中，标有“2013年更新”的条形图表示2012年和2013年的实际数字，远高于2011年绘制该图时的预期。这一急剧增长的部分原因是，PARADIGM项目提供的用户数量远高于最初的预期，而2014年的预期将更低。然而，我们预计2014年半商业接入的可用性将弥补这一减少。

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在JePPIX路线图模型中，预测的市场发展是由大量具有高附加值的中小型应用引起的，而不是由少数低成本的“杀手级”应用引起。该模型为更大的市场容量提供了一条进化之路，这将使晶圆厂能够在一些较小的步骤中提高性能并降低制造过程的成本。这样的成本降低最终也可以实现在大众市场中的低成本应用。

11.结论

基于InP的通用晶圆技术将大大降低有兴趣在新产品或改进产品中应用InP ASPIC的公司的进入成本。它将为许多中小企业带来先进的基于光子InP的集成技术。欧盟和各国政府的重大研发资金使晶圆方法达到了一个水平，即实验性晶圆运行已在工业集成平台上成功演示，晶圆平台的半商业化接入已于2014年开始。在PKD的开发和封装的标准化方面已经取得了重大进展，目前InP PDK支持的元件库比任何其他开放访问的光子集成技术都强大得多。

除了原型设计贯穿多项目晶圆服务之外，我们预计InP在中小型生产方面将极具竞争力。由于生产基础设施的性质，与先进的硅光子学工艺相比，启动成本更低，同时提供了更多的功能。从长远来看，我们预计InP Photonics和CMOS电子器件将合并为异构集成技术，其中CMOS将提供电子功能，InP将提供光子功能。

术语

ADS Advanced Design System (Agilent)

API application programming interface

ASIC application specific IC

ASPIC application specific photonic IC

ASPIC ™ Advanced Simulator for Photonics Integrated Circuits (Filarete)

AWG arrayed waveguide grating

BB building block (used for both BBB and CBB,where the distinction is not relevant)

BBB basic building block

BPM beam propagation method

BOTDR brillouin optical time domain reflectometry

BCB benzocyclobutene

BTB basic technology block

CBB composite building block

CMOS complementary metal–oxide–semiconductor

CMRR common-mode rejection ratio

COBRA Communication technologies; Basic Research and Applications (TU/e research institute)

DBR distributed Bragg reflector

DFB distributed feedback laser

DI delay interferometer

DQPSK differential quadrature phase shift keying

DRC design rule checking

DS downstream

DUT device under test

DUV deep ultra-violet (193 nm)

EAM electro-absorption modulator

E-beam electron-beam

EI electrical isolation section

EME Eigen-mode expansion

e-o electro-optical

ERM electro-refractive (phase) modulator (depletion-type)

ERMI electro-refractive (phase) modulator (injection-type)

ePIXnet European Network of Excellence on Photonic Integrated Components and Circuits,

EuroPIC European manufacturing platform for PhotonicIntegration Circuits

FDTD finite difference time domain

FET field effect transistor

FMW fibre matched waveguide

FP Fabry–Perot

FSR free spectral range

Ge germanium

InGaAs Indium gallium arsenide

InGaAsP Indium gallium arsenide phosphideIC integrated circuit

IIR infinite impulse response

IMOS InP membrane on silicon

InP indium phosphide

IO input–output

IOP PD IOP photonic devices (IOP = Dutch InnovationResearch Project)

IP intellectual property

IPB IP-block

JePPIX Joint European Platform for Photonic Integration of Components and CircuitsLSI large scale integration

MEMPHIS Merging Electronics and Micro and nano Photonics in Integrated Systems, Dutch SmartMix project

MMI multi-mode interference

MFD mode field diameter

MI Michelson interferometer

MIR multimode interference reflector (MMIReflector)

MOVPE metal-organic vapour-phase epitaxy

MPW multi project wafer

MQW multi quantum well

MZI Mach–Zehnder interferometer

OCT optical coherence tomography

PARADIGM Photonic Advanced Research and Development for Integrated Generic Manufacturing

PCB printed circuit board

PD photo detector

PDA photonic design automation

PDK process design kit

PHASAR phased array (early name for AWG)

PIC photonic integrated circuit

PM-DQPSK polarization multiplexing differential quadrature phase-shift keying

POSA PIC optical sub-assembly

PR Polarization rotation section

QD quantum dot

QW quantum well

ROSA receiver optical sub-assembly

RR ring resonator

R&D research & development

SA saturable absorber

SAG selective area growth

SEM scanning electron microscope

Si silicon

SFDR spurious-free dynamic range

SME small or medium enterprise

SOA semiconductor optical amplifier

SOI silicon on insulator

SSC spot size convertor

SSMF standard single mode fiber

STW GTIP Generic Technologies in Integrated Photonics, STW Perspectief Project (STW = Dutch Technology Foundation)

TBR tunable Bragg reflector

TE transverse electric (field)

TEC thermo-electric cooler

Ti-Pt-Au titanium-platinum-gold (contact)

TM transverse magnetic (field)

TOM thermo-optic modulator

TOSA transmitter optical sub assembly

US upstream

VLSI very large scale integration

WDM wavelength division multiplexing

WG waveguide (passive)

WGS deep etched waveguide (strong confinement)

WGT waveguide termination

WGW shallow etched waveguide (weak confinement)

XFP 10 gigabit small form factor pluggable module

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注：本文由天津见合八方光电科技有限公司挑选并翻译，旨在推广和分享相关SOA半导体光放大器基础知识，助力SOA技术的发展和应用。特此告知，本文系经过人工翻译而成，虽本公司尽最大努力保证翻译准确性，但不排除存在误差、遗漏或语义解读导致的不完全准确性，建议读者阅读原文或对照阅读，也欢迎指出错误，共同进步。