0. 环境

- ubuntu18
- vivado 2018.3
- mizar z7010 + ada106模块

1. vivado

1.1 创建vivado工程

运行vivado

source /tools/Xilinx/Vivado/2018.3/settings64.sh
vivado&

创建vivado工程
Vivado -> Create Project -> Next -> 
-> Project name:        linux_sd_adda
-> project location:    /home/xxjianvm/work/mizar/
-> Next

-> RTL Project -> Next
-> Next
-> Next
-> Default part:    xc7z010CLG400-1 -> Next

-> Finish

-> Finish

1.2 建立IP- PS_PL_DAC_8B

130个32位的寄存器定义
序号    定义
0        控制1，PS写，采样频率设置
1        控制2，PS写，高16位是DAC使能，低16位是数据长度
2        回复1，PL写，
3-129    数据，PS写

1.2.1 添加IP

Tools -> Create and Package New IP -> Next

-> Create a new AXI4 peripheral -> Next

    -> Name:        PS_PL_DAC_8B
    -> Description:    PS_READ_WRITE_PL_REG for dac 8 bit
    -> IP location:    /home/xxjianvm/work/mizar/ip_repo
    -> Next
-> Add Interface
    -> Number of Registers:    130
    -> Next
-> Create Peripheral 
    -> Edit IP -> Finish

1.2.2 编辑IP 

1.2.2.1 基本端口定义

双击 PS_PL_DAC_8B_v1_0.v
修改第 17 行

        // Users to add ports here
        input wire clk_50m,
        output wire dac_clk,
        output wire [7:0] dac_data,
        output wire dac_pd,
        
        // User ports ends

修改第 76 行：

        .clk_50m  (   clk_50m ),
        .dac_clk  (   dac_clk ),
        .dac_data (   dac_data),
        .dac_pd   (   dac_pd  )

1.2.2.2 双击 PS_PL_DAC_8B_v1_0_S00_AXI_inst

修改端口，第17行： 

        // Users to add ports here
        input wire clk_50m,
        output wire dac_clk,
        output reg [7:0] dac_data,
        output  wire dac_pd,
        
        
        // User ports ends

slv_reg2改为PL写。注释掉alway模块内的这几行，slv_reg2就改为PS只读不可写。
注释：
//          slv_reg2 <= 0;
注释
//                    slv_reg2[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
注释
//                          slv_reg2 <= slv_reg2;
 
 

1.2.2.3 时钟信号

-> Project Manager -> IP Catalog -> clocking wizard -> 
-> Component Name:    clock
-> Clocking Options 
    -> Input Clock Information 
        -> Primary frequency:    50Mhz

-> Output Clocks
    -> clk_out1: 128MHz
    -> Enable Optional Inputs / Outputs for MMCM/PLL:
        -> 取消勾选lcoked
    -> Reset Type:    Active Low
-> OK -> Generate

1.2.3 编写verilog文件，根据寄存器0，设置时钟

创建文件 da9708_clkswitch.v

这里寄存器0的定义是设置DAC采样频率。为了简便，这个DAC只支持几个64倍数的采样频率。

module da9708_clkswitch
(
	clk_128m, 
	rst_n, 
	slv_reg0,
	
	clk_64m, 
	clk_25p6m,
	clk_12p8m,
	clk_6400k,
	clk_2560k,
	clk_1280k,
	clk_640k,
	clk_256k,
	clk_128k,
	clk_64k,
	clk_25600,
	clk_12800,
	clk_6400,
	clk_2560,
	clk_1280,
	clk_640,
	clk_256,
	clk_128,
	clk_64,
	clk_25p6,
	clk_12p8,
	clk_6p4,
	
	clk_dac
);

input 	wire	clk_128m; 
input 	wire	rst_n;
input	wire	[31:0]	slv_reg0;


input 	wire	clk_64m; 
input 	wire	clk_25p6m;
input 	wire	clk_12p8m;
input 	wire	clk_6400k;
input 	wire	clk_2560k;
input 	wire	clk_1280k;
input 	wire	clk_640k;
input 	wire	clk_256k;
input 	wire	clk_128k;
input	wire		clk_64k;
input 	wire	clk_25600;
input 	wire	clk_12800;
input	wire		clk_6400;
input 	wire	clk_2560;
input 	wire	clk_1280;
input	wire		clk_640;
input 	wire	clk_256;
input 	wire	clk_128;
input	wire		clk_64;
input 	wire	clk_25p6;			// 低速时钟用来判断按键
input 	wire	clk_12p8;
input	wire		clk_6p4;

output reg	clk_dac; 

// 
always @( posedge clk_128m or negedge rst_n) begin
	if( ~rst_n ) begin
		clk_dac <= 1'b0;
	end
	else begin
		if ( slv_reg0 >= 32'd64_000_000 ) begin
			clk_dac <= clk_64m;
		end
		else if ( slv_reg0 >= 32'd25_600_000 ) begin
			clk_dac <= clk_25p6m;
		end
		else if ( slv_reg0 >= 32'd12_800_000 ) begin
			clk_dac <= clk_12p8m;
		end
		else if ( slv_reg0 >= 32'd6_400_000 ) begin
			clk_dac <= clk_6400k;
		end
		else if ( slv_reg0 >= 32'd2_560_000 ) begin
			clk_dac <= clk_2560k;
		end
		else if ( slv_reg0 >= 32'd1_280_000 ) begin
			clk_dac <= clk_1280k;
		end
		else if ( slv_reg0 >= 32'd640_000 ) begin
			clk_dac <= clk_640k;
		end
		else if ( slv_reg0 >= 32'd256_000 ) begin
			clk_dac <= clk_256k;
		end
		else if ( slv_reg0 >= 32'd128_000 ) begin
			clk_dac <= clk_128k;
		end
		else if ( slv_reg0 >= 32'd64_000 ) begin
			clk_dac <= clk_64k;
		end
		else if ( slv_reg0 >= 32'd25_600 ) begin
			clk_dac <= clk_25600;
		end
		else if ( slv_reg0 >= 32'd12_800 ) begin
			clk_dac <= clk_12800;
		end
		else if ( slv_reg0 >= 32'd6400 ) begin
			clk_dac <= clk_6400;
		end
		else if ( slv_reg0 >= 32'd2560 ) begin
			clk_dac <= clk_2560;
		end
		else if ( slv_reg0 >= 32'd1280 ) begin
			clk_dac <= clk_1280;
		end
		else if ( slv_reg0 >= 32'd640 ) begin
			clk_dac <= clk_640;
		end
		else if ( slv_reg0 >= 32'd256 ) begin
			clk_dac <= clk_256;
		end
		else if ( slv_reg0 >= 32'd128 ) begin
			clk_dac <= clk_128;
		end
		else if ( slv_reg0 >= 32'd64 ) begin
			clk_dac <= clk_64;
		end
		else if ( slv_reg0 >= 32'd25 ) begin
			clk_dac <= clk_25p6;
		end
		else if ( slv_reg0 >= 32'd12 ) begin
			clk_dac <= clk_12p8;
		end
		else if ( slv_reg0 >= 32'd6 ) begin
			clk_dac <= clk_6p4;
		end
		else begin
			clk_dac <= 1'b0;
		end
	end
end


endmodule

1.2.4 编写verilog，对128M时钟分频

1.2.4.1 da9708_clkevery.v

module da9708_clkevery
(
	clk_128m, 
	rst_n, 
	clk_64m, 
	clk_25p6m,
	clk_12p8m,
	clk_6400k,
	clk_2560k,
	clk_1280k,
	clk_640k,
	clk_256k,
	clk_128k,
	clk_64k,
	clk_25600,
	clk_12800,
	clk_6400,
	clk_2560,
	clk_1280,
	clk_640,
	clk_256,
	clk_128,
	clk_64,
	clk_25p6,
	clk_12p8,
	clk_6p4
);

input 		clk_128m; 
input 		rst_n;
output 		clk_64m; 
output 		clk_25p6m;
output 		clk_12p8m;
output 		clk_6400k;
output 		clk_2560k;
output 		clk_1280k;
output 		clk_640k;
output 		clk_256k;
output 		clk_128k;
output		clk_64k;
output 		clk_25600;
output 		clk_12800;
output		clk_6400;
output 		clk_2560;
output 		clk_1280;
output		clk_640;
output 		clk_256;
output 		clk_128;
output		clk_64;
output 		clk_25p6;
output 		clk_12p8;
output		clk_6p4;


// 时钟生成模块  64m
clk_div10 clk_div10_inst_0(
	.clk( clk_128m ),
	.rstn( rst_n ) ,
	.clk_div2( clk_64m )
);

// 时钟生成模块  25.6m, 12.8m, 6400k
clk_div2p5 clk_div2p5_inst_1(
	.clk( clk_64m ),
	.rstn( rst_n ) ,
	.clk_div2p5( clk_25p6m )
);
clk_div5 clk_div5_inst_1(
	.clk( clk_64m ),
	.rstn( rst_n ) ,
	.clk_div5( clk_12p8m )
);
clk_div10 clk_div10_inst_1(
	.clk( clk_64m ),
	.rstn( rst_n ) ,
	.clk_div10( clk_6400k )
);

// 时钟生成模块  2560k, 1280k, 640k
clk_div2p5 clk_div2p5_inst_2(
	.clk( clk_6400k ),
	.rstn( rst_n ) ,
	.clk_div2p5( clk_2560k )
);
clk_div5 clk_div5_inst_2(
	.clk( clk_6400k ),
	.rstn( rst_n ) ,
	.clk_div5( clk_1280k )
);
clk_div10 clk_div10_inst_2(
	.clk( clk_6400k ),
	.rstn( rst_n ) ,
	.clk_div10( clk_640k )
);


// 时钟生成模块  256k, 128k, 64k
clk_div2p5 clk_div2p5_inst_3(
	.clk( clk_640k ),
	.rstn( rst_n ) ,
	.clk_div2p5( clk_256k )
);
clk_div5 clk_div5_inst_3(
	.clk( clk_640k ),
	.rstn( rst_n ) ,
	.clk_div5( clk_128k )
);
clk_div10 clk_div10_inst_3(
	.clk( clk_640k ),
	.rstn( rst_n ) ,
	.clk_div10( clk_64k )
);

// 时钟生成模块  25600, 12800, 6400
clk_div2p5 clk_div2p5_inst_4(
	.clk( clk_64k ),
	.rstn( rst_n ) ,
	.clk_div2p5( clk_25600 )
);
clk_div5 clk_div5_inst_4(
	.clk( clk_64k ),
	.rstn( rst_n ) ,
	.clk_div5( clk_12800 )
);
clk_div10 clk_div10_inst_4(
	.clk( clk_64k ),
	.rstn( rst_n ) ,
	.clk_div10( clk_6400 )
);

// 时钟生成模块  2560, 1280, 640
clk_div2p5 clk_div2p5_inst_5(
	.clk( clk_6400 ),
	.rstn( rst_n ) ,
	.clk_div2p5( clk_2560 )
);
clk_div5 clk_div5_inst_5(
	.clk( clk_6400 ),
	.rstn( rst_n ) ,
	.clk_div5( clk_1280 )
);
clk_div10 clk_div10_inst_5(
	.clk( clk_6400 ),
	.rstn( rst_n ) ,
	.clk_div10( clk_640 )
);

// 时钟生成模块  256, 128, 64
clk_div2p5 clk_div2p5_inst_6(
	.clk( clk_640 ),
	.rstn( rst_n ) ,
	.clk_div2p5( clk_256 )
);
clk_div5 clk_div5_inst_6(
	.clk( clk_640 ),
	.rstn( rst_n ) ,
	.clk_div5( clk_128 )
);
clk_div10 clk_div10_inst_6(
	.clk( clk_640 ),
	.rstn( rst_n ) ,
	.clk_div10( clk_64 )
);


// 时钟生成模块  25.6, 12.8, 6.4
clk_div2p5 clk_div2p5_inst_7(
	.clk( clk_64 ),
	.rstn( rst_n ) ,
	.clk_div2p5( clk_25p6 )
);
clk_div5 clk_div5_inst_7(
	.clk( clk_64 ),
	.rstn( rst_n ) ,
	.clk_div5( clk_12p8 )
);
clk_div10 clk_div10_inst_7(
	.clk( clk_64 ),
	.rstn( rst_n ) ,
	.clk_div10( clk_6p4 )
);





endmodule

1.2.4.2 clk_div10.v

网上下载的时钟10分频：

module clk_div10
# (parameter DIV_CLK = 10 )
(
input rstn ,
input clk,
output clk_div2,
output clk_div4,
output clk_div10
);

//2 分频
reg clk_div2_r ;
always @(posedge clk or negedge rstn) begin
if (!rstn) begin
clk_div2_r <= 'b0 ;
end
else begin
clk_div2_r <= ~clk_div2_r ;
end
end
assign clk_div2 = clk_div2_r ;

//4 分频
reg clk_div4_r ;
always @(posedge clk_div2 or negedge rstn) begin
if (!rstn) begin
clk_div4_r <= 'b0 ;
end
else begin
clk_div4_r <= ~clk_div4_r ;
end
end
assign clk_div4 = clk_div4_r ;

//N/2 计数
reg [3:0] cnt ;
always @(posedge clk or negedge rstn) begin
if (!rstn) begin
cnt <= 'b0 ;
end
else if (cnt == (DIV_CLK/2)-1) begin
cnt <= 'b0 ;
end
else begin
cnt <= cnt + 1'b1 ;
end
end

//输出时钟
reg clk_div10_r ;
always @(posedge clk or negedge rstn) begin
if (!rstn) begin
clk_div10_r <= 1'b0 ;
end
else if (cnt == (DIV_CLK/2)-1 ) begin
clk_div10_r <= ~clk_div10_r ;
end
end
assign clk_div10 = clk_div10_r ;
endmodule

 1.2.4.3 clk_div5.v

时钟5分频是网上下载的。

module clk_div5
 #(parameter DIV_CLK = 5)
 (
  input        rstn ,
  input        clk,
  output       clk_div5
  );

 //计数器
 reg [3:0]      cnt ;
 always @(posedge clk or negedge rstn) begin
   if (!rstn) begin
    cnt  <= 'b0 ;
   end
   else if (cnt == DIV_CLK-1) begin
    cnt  <= 'b0 ;
   end
   else begin
    cnt  <= cnt + 1'b1 ;
   end
 end

 //在上升沿产生5分频
 reg         clkp_div5_r ;
 always @(posedge clk or negedge rstn) begin
   if (!rstn) begin
    clkp_div5_r <= 1'b0 ;
   end
   else if (cnt == (DIV_CLK>>1)-1 ) begin //计数4-8位低电平
    clkp_div5_r <= 0 ;
   end
   else if (cnt == DIV_CLK-1) begin //计数 0-3 为高电平
    clkp_div5_r <= 1 ;
   end
 end
 
 //在下降沿产生5分频
 reg         clkn_div5_r ;
 always @(negedge clk or negedge rstn) begin
   if (!rstn) begin
    clkn_div5_r <= 1'b0 ;
   end
   else if (cnt == (DIV_CLK>>1)-1 ) begin 
    clkn_div5_r <= 0 ;
   end
   else if (cnt == DIV_CLK-1) begin 
    clkn_div5_r <= 1 ;
   end
 end

 //或操作，往往使用基本逻辑单元库
 // or (clk_div5, clkp_div5_r, clkn_div5_r) ;
 assign clk_div5 = clkp_div5_r | clkn_div5_r ;

endmodule

1.2.4.4 clk_div2p5.v

时钟 2.5分频

module clk_div2p5(
	input        clk,
	input        rstn ,
	output       clk_div2p5
);

//计数器
parameter      MUL2_DIV_CLK = 5 ;
reg [3:0]      cnt ;
always @(posedge clk or negedge rstn) begin
   if (!rstn) begin
    cnt  <= 'b0 ;
   end
   else if (cnt == MUL2_DIV_CLK-1) begin //计数2倍分频比
    cnt  <= 'b0 ;
   end
   else begin
    cnt  <= cnt + 1'b1 ;
   end
end

 reg         clk_ave_r ;
 always @(posedge clk or negedge rstn) begin
   if (!rstn) begin
    clk_ave_r <= 1'b0 ;
   end
   //first cycle: 4 source clk cycle
   else if (cnt == 0) begin
    clk_ave_r <= 1 ;
   end
   //2nd cycle: 3 source clk cycle
   else if (cnt == (MUL2_DIV_CLK/2)+1) begin
    clk_ave_r <= 1 ;
   end
   else begin
    clk_ave_r <= 0 ;
   end
 end

 //adjust
 reg         clk_adjust_r ;
 always @(negedge clk or negedge rstn) begin
   if (!rstn) begin
    clk_adjust_r <= 1'b0 ;
   end
   //本次时钟只为调整一致的占空比
   else if (cnt == 1) begin
    clk_adjust_r <= 1 ;
   end
   //本次时钟只为调整一致的精确分频比
   else if (cnt == (MUL2_DIV_CLK/2)+1 ) begin
    clk_adjust_r <= 1 ;
   end
   else begin
    clk_adjust_r <= 0 ;
   end
 end

 assign clk_div2p5 = clk_adjust_r | clk_ave_r ;

endmodule

1.2.5 编写dac_clk驱动

dac_clk_sw.v

封装 da9708_clkswitch.v 和 da9708_clkevery.v， 实现根据寄存器0输出dac_clk，dac_clk_sw.v

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date: 02/18/2024 11:40:35 AM
// Design Name: 
// Module Name: dac_clk_sw
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//


module dac_clk_sw(

	clk_128m, 
	rst_n, 
	slv_reg0,
	
	clk_dac
);
    

input 	wire	clk_128m; 
input 	wire 	rst_n;
input	wire [31:0]	slv_reg0;
output 	wire	clk_dac; 
 
// 按键选择模块
da9708_clkswitch da9708_clkswitch_inst	( 
	.clk_128m	(	clk_128m		), 
	.rst_n		(	rst_n			), 
	.slv_reg0		(	slv_reg0			),
	
	
	.clk_64m		(	clk_64m	),
	.clk_25p6m	(	clk_25p6m	),
	.clk_12p8m	(	clk_12p8m	),
	.clk_6400k	(	clk_6400k	),
	.clk_2560k	(	clk_2560k	),
	.clk_1280k	(	clk_1280k	),
	.clk_640k	(	clk_640k		),
	.clk_256k	(	clk_256k		),
	.clk_128k	(	clk_128k		),
	.clk_64k		(	clk_64k		),
	.clk_25600	(	clk_25600	),
	.clk_12800	(	clk_12800	),
	.clk_6400	(	clk_6400		),
	.clk_2560	(	clk_2560		),
	.clk_1280	(	clk_1280		),
	.clk_640		(	clk_640		),
	.clk_256		(	clk_256		),
	.clk_128		(	clk_128		),
	.clk_64		(	clk_64		),
	.clk_25p6	(	clk_25p6		),
	.clk_12p8	(	clk_12p8		),
	.clk_6p4		(	clk_6p4		),
	
	.clk_dac		(	clk_dac		 )
);

// 时钟生成模块
da9708_clkevery da9708_clkevery_inst1(
	.clk_128m	(	clk_128m		), 
	.rst_n		(	rst_n			), 
	
	.clk_64m		(	clk_64m	),
	.clk_25p6m	(	clk_25p6m	),
	.clk_12p8m	(	clk_12p8m	),
	.clk_6400k	(	clk_6400k	),
	.clk_2560k	(	clk_2560k	),
	.clk_1280k	(	clk_1280k	),
	.clk_640k	(	clk_640k		),
	.clk_256k	(	clk_256k		),
	.clk_128k	(	clk_128k		),
	.clk_64k		(	clk_64k		),
	.clk_25600	(	clk_25600	),
	.clk_12800	(	clk_12800	),
	.clk_6400	(	clk_6400		),
	.clk_2560	(	clk_2560		),
	.clk_1280	(	clk_1280		),
	.clk_640		(	clk_640		),
	.clk_256		(	clk_256		),
	.clk_128		(	clk_128		),
	.clk_64		(	clk_64		),
	.clk_25p6	(	clk_25p6		),
	.clk_12p8	(	clk_12p8		),
	.clk_6p4		(	clk_6p4		)
);


endmodule

1.2.6 继续修改 PS_PL_DAC_8B_v1_0_S00_AXI_inst

	// Add user logic here
    clk_wiz_0 inst_clk_wiz_0(
        .clk_in1  (clk_50m ),	        // input clk_in1
        .resetn   (S_AXI_ARESETN  ),    // input reset
        .clk_out1 (clk_128m)            // output clk_out1
    );      
    dac_clk_sw dac_clk_sw_inst(
        .clk_128m          (   clk_128m    ), 
        .rst_n             (   S_AXI_ARESETN  ), 
        .slv_reg0          (   slv_reg0    ),
        .clk_dac           (   dac_clk     )
    );   
    reg [15:0] dac_cnt = 16'd0; 
    always @( posedge dac_clk or negedge S_AXI_ARESETN ) begin
        if ( S_AXI_ARESETN == 1'b0 ) begin
            dac_cnt <= 16'd0;
        end
        else begin
            if ( dac_cnt >= slv_reg1[15:0] - 1'b1 ) begin
                dac_cnt <= 16'd0;
            end
            else begin
                dac_cnt <= dac_cnt + 1'b1;
            end
        end
    end

wire [7:0] dac_buffer [507:0];
assign dac_buffer[	0	] = slv_reg3	[7:0];
assign dac_buffer[	1	] = slv_reg3	[15:8];
assign dac_buffer[	2	] = slv_reg3	[23:16];
assign dac_buffer[	3	] = slv_reg3	[31:24];
assign dac_buffer[	4	] = slv_reg4	[7:0];
assign dac_buffer[	5	] = slv_reg4	[15:8];
assign dac_buffer[	6	] = slv_reg4	[23:16];
assign dac_buffer[	7	] = slv_reg4	[31:24];
assign dac_buffer[	8	] = slv_reg5	[7:0];
assign dac_buffer[	9	] = slv_reg5	[15:8];
assign dac_buffer[	10	] = slv_reg5	[23:16];
assign dac_buffer[	11	] = slv_reg5	[31:24];
assign dac_buffer[	12	] = slv_reg6	[7:0];
assign dac_buffer[	13	] = slv_reg6	[15:8];
assign dac_buffer[	14	] = slv_reg6	[23:16];
assign dac_buffer[	15	] = slv_reg6	[31:24];
assign dac_buffer[	16	] = slv_reg7	[7:0];
assign dac_buffer[	17	] = slv_reg7	[15:8];
assign dac_buffer[	18	] = slv_reg7	[23:16];
assign dac_buffer[	19	] = slv_reg7	[31:24];
assign dac_buffer[	20	] = slv_reg8	[7:0];
assign dac_buffer[	21	] = slv_reg8	[15:8];
assign dac_buffer[	22	] = slv_reg8	[23:16];
assign dac_buffer[	23	] = slv_reg8	[31:24];
assign dac_buffer[	24	] = slv_reg9	[7:0];
assign dac_buffer[	25	] = slv_reg9	[15:8];
assign dac_buffer[	26	] = slv_reg9	[23:16];
assign dac_buffer[	27	] = slv_reg9	[31:24];
assign dac_buffer[	28	] = slv_reg10	[7:0];
assign dac_buffer[	29	] = slv_reg10	[15:8];
assign dac_buffer[	30	] = slv_reg10	[23:16];
assign dac_buffer[	31	] = slv_reg10	[31:24];
assign dac_buffer[	32	] = slv_reg11	[7:0];
assign dac_buffer[	33	] = slv_reg11	[15:8];
assign dac_buffer[	34	] = slv_reg11	[23:16];
assign dac_buffer[	35	] = slv_reg11	[31:24];
assign dac_buffer[	36	] = slv_reg12	[7:0];
assign dac_buffer[	37	] = slv_reg12	[15:8];
assign dac_buffer[	38	] = slv_reg12	[23:16];
assign dac_buffer[	39	] = slv_reg12	[31:24];
assign dac_buffer[	40	] = slv_reg13	[7:0];
assign dac_buffer[	41	] = slv_reg13	[15:8];
assign dac_buffer[	42	] = slv_reg13	[23:16];
assign dac_buffer[	43	] = slv_reg13	[31:24];
assign dac_buffer[	44	] = slv_reg14	[7:0];
assign dac_buffer[	45	] = slv_reg14	[15:8];
assign dac_buffer[	46	] = slv_reg14	[23:16];
assign dac_buffer[	47	] = slv_reg14	[31:24];
assign dac_buffer[	48	] = slv_reg15	[7:0];
assign dac_buffer[	49	] = slv_reg15	[15:8];
assign dac_buffer[	50	] = slv_reg15	[23:16];
assign dac_buffer[	51	] = slv_reg15	[31:24];
assign dac_buffer[	52	] = slv_reg16	[7:0];
assign dac_buffer[	53	] = slv_reg16	[15:8];
assign dac_buffer[	54	] = slv_reg16	[23:16];
assign dac_buffer[	55	] = slv_reg16	[31:24];
assign dac_buffer[	56	] = slv_reg17	[7:0];
assign dac_buffer[	57	] = slv_reg17	[15:8];
assign dac_buffer[	58	] = slv_reg17	[23:16];
assign dac_buffer[	59	] = slv_reg17	[31:24];
assign dac_buffer[	60	] = slv_reg18	[7:0];
assign dac_buffer[	61	] = slv_reg18	[15:8];
assign dac_buffer[	62	] = slv_reg18	[23:16];
assign dac_buffer[	63	] = slv_reg18	[31:24];
assign dac_buffer[	64	] = slv_reg19	[7:0];
assign dac_buffer[	65	] = slv_reg19	[15:8];
assign dac_buffer[	66	] = slv_reg19	[23:16];
assign dac_buffer[	67	] = slv_reg19	[31:24];
assign dac_buffer[	68	] = slv_reg20	[7:0];
assign dac_buffer[	69	] = slv_reg20	[15:8];
assign dac_buffer[	70	] = slv_reg20	[23:16];
assign dac_buffer[	71	] = slv_reg20	[31:24];
assign dac_buffer[	72	] = slv_reg21	[7:0];
assign dac_buffer[	73	] = slv_reg21	[15:8];
assign dac_buffer[	74	] = slv_reg21	[23:16];
assign dac_buffer[	75	] = slv_reg21	[31:24];
assign dac_buffer[	76	] = slv_reg22	[7:0];
assign dac_buffer[	77	] = slv_reg22	[15:8];
assign dac_buffer[	78	] = slv_reg22	[23:16];
assign dac_buffer[	79	] = slv_reg22	[31:24];
assign dac_buffer[	80	] = slv_reg23	[7:0];
assign dac_buffer[	81	] = slv_reg23	[15:8];
assign dac_buffer[	82	] = slv_reg23	[23:16];
assign dac_buffer[	83	] = slv_reg23	[31:24];
assign dac_buffer[	84	] = slv_reg24	[7:0];
assign dac_buffer[	85	] = slv_reg24	[15:8];
assign dac_buffer[	86	] = slv_reg24	[23:16];
assign dac_buffer[	87	] = slv_reg24	[31:24];
assign dac_buffer[	88	] = slv_reg25	[7:0];
assign dac_buffer[	89	] = slv_reg25	[15:8];
assign dac_buffer[	90	] = slv_reg25	[23:16];
assign dac_buffer[	91	] = slv_reg25	[31:24];
assign dac_buffer[	92	] = slv_reg26	[7:0];
assign dac_buffer[	93	] = slv_reg26	[15:8];
assign dac_buffer[	94	] = slv_reg26	[23:16];
assign dac_buffer[	95	] = slv_reg26	[31:24];
assign dac_buffer[	96	] = slv_reg27	[7:0];
assign dac_buffer[	97	] = slv_reg27	[15:8];
assign dac_buffer[	98	] = slv_reg27	[23:16];
assign dac_buffer[	99	] = slv_reg27	[31:24];
assign dac_buffer[	100	] = slv_reg28	[7:0];
assign dac_buffer[	101	] = slv_reg28	[15:8];
assign dac_buffer[	102	] = slv_reg28	[23:16];
assign dac_buffer[	103	] = slv_reg28	[31:24];
assign dac_buffer[	104	] = slv_reg29	[7:0];
assign dac_buffer[	105	] = slv_reg29	[15:8];
assign dac_buffer[	106	] = slv_reg29	[23:16];
assign dac_buffer[	107	] = slv_reg29	[31:24];
assign dac_buffer[	108	] = slv_reg30	[7:0];
assign dac_buffer[	109	] = slv_reg30	[15:8];
assign dac_buffer[	110	] = slv_reg30	[23:16];
assign dac_buffer[	111	] = slv_reg30	[31:24];
assign dac_buffer[	112	] = slv_reg31	[7:0];
assign dac_buffer[	113	] = slv_reg31	[15:8];
assign dac_buffer[	114	] = slv_reg31	[23:16];
assign dac_buffer[	115	] = slv_reg31	[31:24];
assign dac_buffer[	116	] = slv_reg32	[7:0];
assign dac_buffer[	117	] = slv_reg32	[15:8];
assign dac_buffer[	118	] = slv_reg32	[23:16];
assign dac_buffer[	119	] = slv_reg32	[31:24];
assign dac_buffer[	120	] = slv_reg33	[7:0];
assign dac_buffer[	121	] = slv_reg33	[15:8];
assign dac_buffer[	122	] = slv_reg33	[23:16];
assign dac_buffer[	123	] = slv_reg33	[31:24];
assign dac_buffer[	124	] = slv_reg34	[7:0];
assign dac_buffer[	125	] = slv_reg34	[15:8];
assign dac_buffer[	126	] = slv_reg34	[23:16];
assign dac_buffer[	127	] = slv_reg34	[31:24];
assign dac_buffer[	128	] = slv_reg35	[7:0];
assign dac_buffer[	129	] = slv_reg35	[15:8];
assign dac_buffer[	130	] = slv_reg35	[23:16];
assign dac_buffer[	131	] = slv_reg35	[31:24];
assign dac_buffer[	132	] = slv_reg36	[7:0];
assign dac_buffer[	133	] = slv_reg36	[15:8];
assign dac_buffer[	134	] = slv_reg36	[23:16];
assign dac_buffer[	135	] = slv_reg36	[31:24];
assign dac_buffer[	136	] = slv_reg37	[7:0];
assign dac_buffer[	137	] = slv_reg37	[15:8];
assign dac_buffer[	138	] = slv_reg37	[23:16];
assign dac_buffer[	139	] = slv_reg37	[31:24];
assign dac_buffer[	140	] = slv_reg38	[7:0];
assign dac_buffer[	141	] = slv_reg38	[15:8];
assign dac_buffer[	142	] = slv_reg38	[23:16];
assign dac_buffer[	143	] = slv_reg38	[31:24];
assign dac_buffer[	144	] = slv_reg39	[7:0];
assign dac_buffer[	145	] = slv_reg39	[15:8];
assign dac_buffer[	146	] = slv_reg39	[23:16];
assign dac_buffer[	147	] = slv_reg39	[31:24];
assign dac_buffer[	148	] = slv_reg40	[7:0];
assign dac_buffer[	149	] = slv_reg40	[15:8];
assign dac_buffer[	150	] = slv_reg40	[23:16];
assign dac_buffer[	151	] = slv_reg40	[31:24];
assign dac_buffer[	152	] = slv_reg41	[7:0];
assign dac_buffer[	153	] = slv_reg41	[15:8];
assign dac_buffer[	154	] = slv_reg41	[23:16];
assign dac_buffer[	155	] = slv_reg41	[31:24];
assign dac_buffer[	156	] = slv_reg42	[7:0];
assign dac_buffer[	157	] = slv_reg42	[15:8];
assign dac_buffer[	158	] = slv_reg42	[23:16];
assign dac_buffer[	159	] = slv_reg42	[31:24];
assign dac_buffer[	160	] = slv_reg43	[7:0];
assign dac_buffer[	161	] = slv_reg43	[15:8];
assign dac_buffer[	162	] = slv_reg43	[23:16];
assign dac_buffer[	163	] = slv_reg43	[31:24];
assign dac_buffer[	164	] = slv_reg44	[7:0];
assign dac_buffer[	165	] = slv_reg44	[15:8];
assign dac_buffer[	166	] = slv_reg44	[23:16];
assign dac_buffer[	167	] = slv_reg44	[31:24];
assign dac_buffer[	168	] = slv_reg45	[7:0];
assign dac_buffer[	169	] = slv_reg45	[15:8];
assign dac_buffer[	170	] = slv_reg45	[23:16];
assign dac_buffer[	171	] = slv_reg45	[31:24];
assign dac_buffer[	172	] = slv_reg46	[7:0];
assign dac_buffer[	173	] = slv_reg46	[15:8];
assign dac_buffer[	174	] = slv_reg46	[23:16];
assign dac_buffer[	175	] = slv_reg46	[31:24];
assign dac_buffer[	176	] = slv_reg47	[7:0];
assign dac_buffer[	177	] = slv_reg47	[15:8];
assign dac_buffer[	178	] = slv_reg47	[23:16];
assign dac_buffer[	179	] = slv_reg47	[31:24];
assign dac_buffer[	180	] = slv_reg48	[7:0];
assign dac_buffer[	181	] = slv_reg48	[15:8];
assign dac_buffer[	182	] = slv_reg48	[23:16];
assign dac_buffer[	183	] = slv_reg48	[31:24];
assign dac_buffer[	184	] = slv_reg49	[7:0];
assign dac_buffer[	185	] = slv_reg49	[15:8];
assign dac_buffer[	186	] = slv_reg49	[23:16];
assign dac_buffer[	187	] = slv_reg49	[31:24];
assign dac_buffer[	188	] = slv_reg50	[7:0];
assign dac_buffer[	189	] = slv_reg50	[15:8];
assign dac_buffer[	190	] = slv_reg50	[23:16];
assign dac_buffer[	191	] = slv_reg50	[31:24];
assign dac_buffer[	192	] = slv_reg51	[7:0];
assign dac_buffer[	193	] = slv_reg51	[15:8];
assign dac_buffer[	194	] = slv_reg51	[23:16];
assign dac_buffer[	195	] = slv_reg51	[31:24];
assign dac_buffer[	196	] = slv_reg52	[7:0];
assign dac_buffer[	197	] = slv_reg52	[15:8];
assign dac_buffer[	198	] = slv_reg52	[23:16];
assign dac_buffer[	199	] = slv_reg52	[31:24];
assign dac_buffer[	200	] = slv_reg53	[7:0];
assign dac_buffer[	201	] = slv_reg53	[15:8];
assign dac_buffer[	202	] = slv_reg53	[23:16];
assign dac_buffer[	203	] = slv_reg53	[31:24];
assign dac_buffer[	204	] = slv_reg54	[7:0];
assign dac_buffer[	205	] = slv_reg54	[15:8];
assign dac_buffer[	206	] = slv_reg54	[23:16];
assign dac_buffer[	207	] = slv_reg54	[31:24];
assign dac_buffer[	208	] = slv_reg55	[7:0];
assign dac_buffer[	209	] = slv_reg55	[15:8];
assign dac_buffer[	210	] = slv_reg55	[23:16];
assign dac_buffer[	211	] = slv_reg55	[31:24];
assign dac_buffer[	212	] = slv_reg56	[7:0];
assign dac_buffer[	213	] = slv_reg56	[15:8];
assign dac_buffer[	214	] = slv_reg56	[23:16];
assign dac_buffer[	215	] = slv_reg56	[31:24];
assign dac_buffer[	216	] = slv_reg57	[7:0];
assign dac_buffer[	217	] = slv_reg57	[15:8];
assign dac_buffer[	218	] = slv_reg57	[23:16];
assign dac_buffer[	219	] = slv_reg57	[31:24];
assign dac_buffer[	220	] = slv_reg58	[7:0];
assign dac_buffer[	221	] = slv_reg58	[15:8];
assign dac_buffer[	222	] = slv_reg58	[23:16];
assign dac_buffer[	223	] = slv_reg58	[31:24];
assign dac_buffer[	224	] = slv_reg59	[7:0];
assign dac_buffer[	225	] = slv_reg59	[15:8];
assign dac_buffer[	226	] = slv_reg59	[23:16];
assign dac_buffer[	227	] = slv_reg59	[31:24];
assign dac_buffer[	228	] = slv_reg60	[7:0];
assign dac_buffer[	229	] = slv_reg60	[15:8];
assign dac_buffer[	230	] = slv_reg60	[23:16];
assign dac_buffer[	231	] = slv_reg60	[31:24];
assign dac_buffer[	232	] = slv_reg61	[7:0];
assign dac_buffer[	233	] = slv_reg61	[15:8];
assign dac_buffer[	234	] = slv_reg61	[23:16];
assign dac_buffer[	235	] = slv_reg61	[31:24];
assign dac_buffer[	236	] = slv_reg62	[7:0];
assign dac_buffer[	237	] = slv_reg62	[15:8];
assign dac_buffer[	238	] = slv_reg62	[23:16];
assign dac_buffer[	239	] = slv_reg62	[31:24];
assign dac_buffer[	240	] = slv_reg63	[7:0];
assign dac_buffer[	241	] = slv_reg63	[15:8];
assign dac_buffer[	242	] = slv_reg63	[23:16];
assign dac_buffer[	243	] = slv_reg63	[31:24];
assign dac_buffer[	244	] = slv_reg64	[7:0];
assign dac_buffer[	245	] = slv_reg64	[15:8];
assign dac_buffer[	246	] = slv_reg64	[23:16];
assign dac_buffer[	247	] = slv_reg64	[31:24];
assign dac_buffer[	248	] = slv_reg65	[7:0];
assign dac_buffer[	249	] = slv_reg65	[15:8];
assign dac_buffer[	250	] = slv_reg65	[23:16];
assign dac_buffer[	251	] = slv_reg65	[31:24];
assign dac_buffer[	252	] = slv_reg66	[7:0];
assign dac_buffer[	253	] = slv_reg66	[15:8];
assign dac_buffer[	254	] = slv_reg66	[23:16];
assign dac_buffer[	255	] = slv_reg66	[31:24];
assign dac_buffer[	256	] = slv_reg67	[7:0];
assign dac_buffer[	257	] = slv_reg67	[15:8];
assign dac_buffer[	258	] = slv_reg67	[23:16];
assign dac_buffer[	259	] = slv_reg67	[31:24];
assign dac_buffer[	260	] = slv_reg68	[7:0];
assign dac_buffer[	261	] = slv_reg68	[15:8];
assign dac_buffer[	262	] = slv_reg68	[23:16];
assign dac_buffer[	263	] = slv_reg68	[31:24];
assign dac_buffer[	264	] = slv_reg69	[7:0];
assign dac_buffer[	265	] = slv_reg69	[15:8];
assign dac_buffer[	266	] = slv_reg69	[23:16];
assign dac_buffer[	267	] = slv_reg69	[31:24];
assign dac_buffer[	268	] = slv_reg70	[7:0];
assign dac_buffer[	269	] = slv_reg70	[15:8];
assign dac_buffer[	270	] = slv_reg70	[23:16];
assign dac_buffer[	271	] = slv_reg70	[31:24];
assign dac_buffer[	272	] = slv_reg71	[7:0];
assign dac_buffer[	273	] = slv_reg71	[15:8];
assign dac_buffer[	274	] = slv_reg71	[23:16];
assign dac_buffer[	275	] = slv_reg71	[31:24];
assign dac_buffer[	276	] = slv_reg72	[7:0];
assign dac_buffer[	277	] = slv_reg72	[15:8];
assign dac_buffer[	278	] = slv_reg72	[23:16];
assign dac_buffer[	279	] = slv_reg72	[31:24];
assign dac_buffer[	280	] = slv_reg73	[7:0];
assign dac_buffer[	281	] = slv_reg73	[15:8];
assign dac_buffer[	282	] = slv_reg73	[23:16];
assign dac_buffer[	283	] = slv_reg73	[31:24];
assign dac_buffer[	284	] = slv_reg74	[7:0];
assign dac_buffer[	285	] = slv_reg74	[15:8];
assign dac_buffer[	286	] = slv_reg74	[23:16];
assign dac_buffer[	287	] = slv_reg74	[31:24];
assign dac_buffer[	288	] = slv_reg75	[7:0];
assign dac_buffer[	289	] = slv_reg75	[15:8];
assign dac_buffer[	290	] = slv_reg75	[23:16];
assign dac_buffer[	291	] = slv_reg75	[31:24];
assign dac_buffer[	292	] = slv_reg76	[7:0];
assign dac_buffer[	293	] = slv_reg76	[15:8];
assign dac_buffer[	294	] = slv_reg76	[23:16];
assign dac_buffer[	295	] = slv_reg76	[31:24];
assign dac_buffer[	296	] = slv_reg77	[7:0];
assign dac_buffer[	297	] = slv_reg77	[15:8];
assign dac_buffer[	298	] = slv_reg77	[23:16];
assign dac_buffer[	299	] = slv_reg77	[31:24];
assign dac_buffer[	300	] = slv_reg78	[7:0];
assign dac_buffer[	301	] = slv_reg78	[15:8];
assign dac_buffer[	302	] = slv_reg78	[23:16];
assign dac_buffer[	303	] = slv_reg78	[31:24];
assign dac_buffer[	304	] = slv_reg79	[7:0];
assign dac_buffer[	305	] = slv_reg79	[15:8];
assign dac_buffer[	306	] = slv_reg79	[23:16];
assign dac_buffer[	307	] = slv_reg79	[31:24];
assign dac_buffer[	308	] = slv_reg80	[7:0];
assign dac_buffer[	309	] = slv_reg80	[15:8];
assign dac_buffer[	310	] = slv_reg80	[23:16];
assign dac_buffer[	311	] = slv_reg80	[31:24];
assign dac_buffer[	312	] = slv_reg81	[7:0];
assign dac_buffer[	313	] = slv_reg81	[15:8];
assign dac_buffer[	314	] = slv_reg81	[23:16];
assign dac_buffer[	315	] = slv_reg81	[31:24];
assign dac_buffer[	316	] = slv_reg82	[7:0];
assign dac_buffer[	317	] = slv_reg82	[15:8];
assign dac_buffer[	318	] = slv_reg82	[23:16];
assign dac_buffer[	319	] = slv_reg82	[31:24];
assign dac_buffer[	320	] = slv_reg83	[7:0];
assign dac_buffer[	321	] = slv_reg83	[15:8];
assign dac_buffer[	322	] = slv_reg83	[23:16];
assign dac_buffer[	323	] = slv_reg83	[31:24];
assign dac_buffer[	324	] = slv_reg84	[7:0];
assign dac_buffer[	325	] = slv_reg84	[15:8];
assign dac_buffer[	326	] = slv_reg84	[23:16];
assign dac_buffer[	327	] = slv_reg84	[31:24];
assign dac_buffer[	328	] = slv_reg85	[7:0];
assign dac_buffer[	329	] = slv_reg85	[15:8];
assign dac_buffer[	330	] = slv_reg85	[23:16];
assign dac_buffer[	331	] = slv_reg85	[31:24];
assign dac_buffer[	332	] = slv_reg86	[7:0];
assign dac_buffer[	333	] = slv_reg86	[15:8];
assign dac_buffer[	334	] = slv_reg86	[23:16];
assign dac_buffer[	335	] = slv_reg86	[31:24];
assign dac_buffer[	336	] = slv_reg87	[7:0];
assign dac_buffer[	337	] = slv_reg87	[15:8];
assign dac_buffer[	338	] = slv_reg87	[23:16];
assign dac_buffer[	339	] = slv_reg87	[31:24];
assign dac_buffer[	340	] = slv_reg88	[7:0];
assign dac_buffer[	341	] = slv_reg88	[15:8];
assign dac_buffer[	342	] = slv_reg88	[23:16];
assign dac_buffer[	343	] = slv_reg88	[31:24];
assign dac_buffer[	344	] = slv_reg89	[7:0];
assign dac_buffer[	345	] = slv_reg89	[15:8];
assign dac_buffer[	346	] = slv_reg89	[23:16];
assign dac_buffer[	347	] = slv_reg89	[31:24];
assign dac_buffer[	348	] = slv_reg90	[7:0];
assign dac_buffer[	349	] = slv_reg90	[15:8];
assign dac_buffer[	350	] = slv_reg90	[23:16];
assign dac_buffer[	351	] = slv_reg90	[31:24];
assign dac_buffer[	352	] = slv_reg91	[7:0];
assign dac_buffer[	353	] = slv_reg91	[15:8];
assign dac_buffer[	354	] = slv_reg91	[23:16];
assign dac_buffer[	355	] = slv_reg91	[31:24];
assign dac_buffer[	356	] = slv_reg92	[7:0];
assign dac_buffer[	357	] = slv_reg92	[15:8];
assign dac_buffer[	358	] = slv_reg92	[23:16];
assign dac_buffer[	359	] = slv_reg92	[31:24];
assign dac_buffer[	360	] = slv_reg93	[7:0];
assign dac_buffer[	361	] = slv_reg93	[15:8];
assign dac_buffer[	362	] = slv_reg93	[23:16];
assign dac_buffer[	363	] = slv_reg93	[31:24];
assign dac_buffer[	364	] = slv_reg94	[7:0];
assign dac_buffer[	365	] = slv_reg94	[15:8];
assign dac_buffer[	366	] = slv_reg94	[23:16];
assign dac_buffer[	367	] = slv_reg94	[31:24];
assign dac_buffer[	368	] = slv_reg95	[7:0];
assign dac_buffer[	369	] = slv_reg95	[15:8];
assign dac_buffer[	370	] = slv_reg95	[23:16];
assign dac_buffer[	371	] = slv_reg95	[31:24];
assign dac_buffer[	372	] = slv_reg96	[7:0];
assign dac_buffer[	373	] = slv_reg96	[15:8];
assign dac_buffer[	374	] = slv_reg96	[23:16];
assign dac_buffer[	375	] = slv_reg96	[31:24];
assign dac_buffer[	376	] = slv_reg97	[7:0];
assign dac_buffer[	377	] = slv_reg97	[15:8];
assign dac_buffer[	378	] = slv_reg97	[23:16];
assign dac_buffer[	379	] = slv_reg97	[31:24];
assign dac_buffer[	380	] = slv_reg98	[7:0];
assign dac_buffer[	381	] = slv_reg98	[15:8];
assign dac_buffer[	382	] = slv_reg98	[23:16];
assign dac_buffer[	383	] = slv_reg98	[31:24];
assign dac_buffer[	384	] = slv_reg99	[7:0];
assign dac_buffer[	385	] = slv_reg99	[15:8];
assign dac_buffer[	386	] = slv_reg99	[23:16];
assign dac_buffer[	387	] = slv_reg99	[31:24];
assign dac_buffer[	388	] = slv_reg100	[7:0];
assign dac_buffer[	389	] = slv_reg100	[15:8];
assign dac_buffer[	390	] = slv_reg100	[23:16];
assign dac_buffer[	391	] = slv_reg100	[31:24];
assign dac_buffer[	392	] = slv_reg101	[7:0];
assign dac_buffer[	393	] = slv_reg101	[15:8];
assign dac_buffer[	394	] = slv_reg101	[23:16];
assign dac_buffer[	395	] = slv_reg101	[31:24];
assign dac_buffer[	396	] = slv_reg102	[7:0];
assign dac_buffer[	397	] = slv_reg102	[15:8];
assign dac_buffer[	398	] = slv_reg102	[23:16];
assign dac_buffer[	399	] = slv_reg102	[31:24];
assign dac_buffer[	400	] = slv_reg103	[7:0];
assign dac_buffer[	401	] = slv_reg103	[15:8];
assign dac_buffer[	402	] = slv_reg103	[23:16];
assign dac_buffer[	403	] = slv_reg103	[31:24];
assign dac_buffer[	404	] = slv_reg104	[7:0];
assign dac_buffer[	405	] = slv_reg104	[15:8];
assign dac_buffer[	406	] = slv_reg104	[23:16];
assign dac_buffer[	407	] = slv_reg104	[31:24];
assign dac_buffer[	408	] = slv_reg105	[7:0];
assign dac_buffer[	409	] = slv_reg105	[15:8];
assign dac_buffer[	410	] = slv_reg105	[23:16];
assign dac_buffer[	411	] = slv_reg105	[31:24];
assign dac_buffer[	412	] = slv_reg106	[7:0];
assign dac_buffer[	413	] = slv_reg106	[15:8];
assign dac_buffer[	414	] = slv_reg106	[23:16];
assign dac_buffer[	415	] = slv_reg106	[31:24];
assign dac_buffer[	416	] = slv_reg107	[7:0];
assign dac_buffer[	417	] = slv_reg107	[15:8];
assign dac_buffer[	418	] = slv_reg107	[23:16];
assign dac_buffer[	419	] = slv_reg107	[31:24];
assign dac_buffer[	420	] = slv_reg108	[7:0];
assign dac_buffer[	421	] = slv_reg108	[15:8];
assign dac_buffer[	422	] = slv_reg108	[23:16];
assign dac_buffer[	423	] = slv_reg108	[31:24];
assign dac_buffer[	424	] = slv_reg109	[7:0];
assign dac_buffer[	425	] = slv_reg109	[15:8];
assign dac_buffer[	426	] = slv_reg109	[23:16];
assign dac_buffer[	427	] = slv_reg109	[31:24];
assign dac_buffer[	428	] = slv_reg110	[7:0];
assign dac_buffer[	429	] = slv_reg110	[15:8];
assign dac_buffer[	430	] = slv_reg110	[23:16];
assign dac_buffer[	431	] = slv_reg110	[31:24];
assign dac_buffer[	432	] = slv_reg111	[7:0];
assign dac_buffer[	433	] = slv_reg111	[15:8];
assign dac_buffer[	434	] = slv_reg111	[23:16];
assign dac_buffer[	435	] = slv_reg111	[31:24];
assign dac_buffer[	436	] = slv_reg112	[7:0];
assign dac_buffer[	437	] = slv_reg112	[15:8];
assign dac_buffer[	438	] = slv_reg112	[23:16];
assign dac_buffer[	439	] = slv_reg112	[31:24];
assign dac_buffer[	440	] = slv_reg113	[7:0];
assign dac_buffer[	441	] = slv_reg113	[15:8];
assign dac_buffer[	442	] = slv_reg113	[23:16];
assign dac_buffer[	443	] = slv_reg113	[31:24];
assign dac_buffer[	444	] = slv_reg114	[7:0];
assign dac_buffer[	445	] = slv_reg114	[15:8];
assign dac_buffer[	446	] = slv_reg114	[23:16];
assign dac_buffer[	447	] = slv_reg114	[31:24];
assign dac_buffer[	448	] = slv_reg115	[7:0];
assign dac_buffer[	449	] = slv_reg115	[15:8];
assign dac_buffer[	450	] = slv_reg115	[23:16];
assign dac_buffer[	451	] = slv_reg115	[31:24];
assign dac_buffer[	452	] = slv_reg116	[7:0];
assign dac_buffer[	453	] = slv_reg116	[15:8];
assign dac_buffer[	454	] = slv_reg116	[23:16];
assign dac_buffer[	455	] = slv_reg116	[31:24];
assign dac_buffer[	456	] = slv_reg117	[7:0];
assign dac_buffer[	457	] = slv_reg117	[15:8];
assign dac_buffer[	458	] = slv_reg117	[23:16];
assign dac_buffer[	459	] = slv_reg117	[31:24];
assign dac_buffer[	460	] = slv_reg118	[7:0];
assign dac_buffer[	461	] = slv_reg118	[15:8];
assign dac_buffer[	462	] = slv_reg118	[23:16];
assign dac_buffer[	463	] = slv_reg118	[31:24];
assign dac_buffer[	464	] = slv_reg119	[7:0];
assign dac_buffer[	465	] = slv_reg119	[15:8];
assign dac_buffer[	466	] = slv_reg119	[23:16];
assign dac_buffer[	467	] = slv_reg119	[31:24];
assign dac_buffer[	468	] = slv_reg120	[7:0];
assign dac_buffer[	469	] = slv_reg120	[15:8];
assign dac_buffer[	470	] = slv_reg120	[23:16];
assign dac_buffer[	471	] = slv_reg120	[31:24];
assign dac_buffer[	472	] = slv_reg121	[7:0];
assign dac_buffer[	473	] = slv_reg121	[15:8];
assign dac_buffer[	474	] = slv_reg121	[23:16];
assign dac_buffer[	475	] = slv_reg121	[31:24];
assign dac_buffer[	476	] = slv_reg122	[7:0];
assign dac_buffer[	477	] = slv_reg122	[15:8];
assign dac_buffer[	478	] = slv_reg122	[23:16];
assign dac_buffer[	479	] = slv_reg122	[31:24];
assign dac_buffer[	480	] = slv_reg123	[7:0];
assign dac_buffer[	481	] = slv_reg123	[15:8];
assign dac_buffer[	482	] = slv_reg123	[23:16];
assign dac_buffer[	483	] = slv_reg123	[31:24];
assign dac_buffer[	484	] = slv_reg124	[7:0];
assign dac_buffer[	485	] = slv_reg124	[15:8];
assign dac_buffer[	486	] = slv_reg124	[23:16];
assign dac_buffer[	487	] = slv_reg124	[31:24];
assign dac_buffer[	488	] = slv_reg125	[7:0];
assign dac_buffer[	489	] = slv_reg125	[15:8];
assign dac_buffer[	490	] = slv_reg125	[23:16];
assign dac_buffer[	491	] = slv_reg125	[31:24];
assign dac_buffer[	492	] = slv_reg126	[7:0];
assign dac_buffer[	493	] = slv_reg126	[15:8];
assign dac_buffer[	494	] = slv_reg126	[23:16];
assign dac_buffer[	495	] = slv_reg126	[31:24];
assign dac_buffer[	496	] = slv_reg127	[7:0];
assign dac_buffer[	497	] = slv_reg127	[15:8];
assign dac_buffer[	498	] = slv_reg127	[23:16];
assign dac_buffer[	499	] = slv_reg127	[31:24];
assign dac_buffer[	500	] = slv_reg128	[7:0];
assign dac_buffer[	501	] = slv_reg128	[15:8];
assign dac_buffer[	502	] = slv_reg128	[23:16];
assign dac_buffer[	503	] = slv_reg128	[31:24];
assign dac_buffer[	504	] = slv_reg129	[7:0];
assign dac_buffer[	505	] = slv_reg129	[15:8];
assign dac_buffer[	506	] = slv_reg129	[23:16];
assign dac_buffer[	507	] = slv_reg129	[31:24];


    
    always @( posedge dac_clk ) begin
        if ( slv_reg1[16] == 1'b0 ) begin
            dac_data <= 8'd0;
        end
        else begin
            dac_data <= dac_buffer[dac_cnt];
        end
    end
    assign dac_pd = ~slv_reg1[16];
    
	// User logic ends

1.2.7 打包

PROJECT MANAGER -> Edit Package IP - PS_PL_DAC_8B -> 
    -> File Groups -> Merge changes from File Groups Wizard

    -> Customization Parameters -> Merge changes from File Groups Wizard
    -> Review and Package -> Re-Package IP

1.3 建立IP- PS_PL_ADC_8B

130个32位的寄存器定义
序号    定义
0        控制1，PS写，采样频率设置
1        控制2，PS写，高16位是采样状态控制，低16位是采样数量
2        回复1，PL写，
3-129    数据，PL写

本程序ADC采样是这样的交互过程：

PS：设置控制2为0001xxxx，空闲
PL：设置回复1为0001xxxx，空闲
PS：设置控制2为0002xxxx，开始采样
PL：设置回复1为0002xxxx，开始采样
PL：设置回复1为0004xxxx，采样完毕
PS：设置控制2为0004xxxx，采样完毕

1.3.1 添加IP

Tools -> Create and Package New IP -> Next
-> Create a new AXI4 peripheral -> Next
    -> Name:        PS_PL_ADC_8B
    -> Description:    PS_READ_WRITE_PL_REG for adc 8 bit
    -> IP location:    /home/xxjianvm/work/mizar/ip_repo
    -> Next
-> Add Interface
    -> Number of Registers:    130
    -> Next
-> Create Peripheral 
    -> Edit IP -> Finish

1.3.2 编辑模块端口 PS_PL_ADC_8B_v1_0.v

修改第 17 行

        // Users to add ports here
        input wire clk_50m,
        output wire adc_clk,
        input wire [7:0] adc_data,
        output  wire adc_pd,
        
        // User ports ends

修改第 76 行：

       .clk_50m  (   clk_50m ),
        .adc_clk  (   adc_clk ),
        .adc_data (   adc_data),
        .adc_pd   (   adc_pd  )

1.3.3 编辑PS_PL_ADC_8B_v1_0_S00_AXI_inst
修改端口，第17行： 

        // Users to add ports here
        input wire clk_50m,
        output wire adc_clk,
        input wire [7:0] adc_data,
        output  wire adc_pd,
        
        
        // User ports ends

把slv_reg2 - slv_reg511改为PL写。

把图示的always模块内的slv_reg2 - slv_reg129 都注释掉，变成PL读写，PS只读。

注释：
//          slv_reg2 <= 0;
注释
//                    slv_reg2[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
注释
//                          slv_reg2 <= slv_reg2;
注意 slv_reg2 - slv_reg129 都要注释。

1.3.3 编写 clk_div.v

对 50MHz的时钟分频

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date: 02/18/2024 02:04:13 PM
// Design Name: 
// Module Name: clk_div
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//


module clk_div(
	clk_50m, 
	rst_n,
	clk_20m,
	clk_10m,
	clk_8m,
	clk_5m,
	clk_4m,
	clk_2m,
	clk_1m,
	clk_800k,
	clk_400k,
	clk_200k,
	clk_100k,
	clk_80k,
	clk_40k,
	clk_20k,
	clk_10k,
	clk_8k,
	clk_4k,
	clk_2k,
	clk_1k,
	clk_800,
	clk_400,
	clk_200,
	clk_100
	 
    );
    
input 	wire	clk_50m; 
input 	wire	rst_n;
output  wire    clk_20m;
output  wire    clk_10m;
output  wire    clk_8m;
output  wire    clk_5m;
output  wire    clk_4m;
output  wire    clk_2m;
output  wire    clk_1m;
output  wire    clk_800k;
output  wire    clk_400k;
output  wire    clk_200k;
output  wire    clk_100k;
output  wire    clk_80k;
output  wire    clk_40k;
output  wire    clk_20k;
output  wire    clk_10k;
output  wire    clk_8k;
output  wire    clk_4k;
output  wire    clk_2k;
output  wire    clk_1k;
output  wire    clk_800;
output  wire    clk_400;
output  wire    clk_200;
output  wire    clk_100;


// 时钟生成模块  20m, 10m, 5m
clk_div2p5 clk_gen_20m(
	.clk       ( clk_50m ),
	.rstn      ( rst_n   ) ,
	.clk_div2p5( clk_20m )
);
clk_div5 clk_gen_10m(
	.clk       ( clk_50m ),
	.rstn      ( rst_n   ) ,
	.clk_div5  ( clk_10m )
);
clk_div10 clk_gen_5m(
	.clk       ( clk_50m ),
	.rstn      ( rst_n   ) ,
	.clk_div10 ( clk_5m )
);

// 时钟生成模块  8m, 4m, 2m
clk_div2p5 clk_gen_8m(
	.clk       ( clk_20m ),
	.rstn      ( rst_n   ) ,
	.clk_div2p5( clk_8m )
);
clk_div5 clk_gen_4m(
	.clk       ( clk_20m ),
	.rstn      ( rst_n   ) ,
	.clk_div5  ( clk_4m )
);
clk_div10 clk_gen_2m(
	.clk       ( clk_20m ),
	.rstn      ( rst_n   ) ,
	.clk_div10 ( clk_2m )
);

// 时钟生成模块  1m
clk_div10 clk_gen_1m(
	.clk       ( clk_10m ),
	.rstn      ( rst_n   ) ,
	.clk_div10 ( clk_1m )
);
// 时钟生成模块  800k
clk_div2p5 clk_gen_800k(
	.clk       ( clk_2m ),
	.rstn      ( rst_n   ) ,
	.clk_div2p5( clk_800k )
);
// 时钟生成模块  400k, 200k, 100k
clk_div2p5 clk_gen_400k(
	.clk       ( clk_1m ),
	.rstn      ( rst_n   ) ,
	.clk_div2p5( clk_400k )
);
clk_div5 clk_gen_200k(
	.clk       ( clk_1m ),
	.rstn      ( rst_n   ) ,
	.clk_div5  ( clk_200k )
);
clk_div10 clk_gen_100k(
	.clk       ( clk_1m ),
	.rstn      ( rst_n   ) ,
	.clk_div10 ( clk_100k )
);
// 时钟生成模块  80k
clk_div2p5 clk_gen_80k(
	.clk       ( clk_200k ),
	.rstn      ( rst_n   ) ,
	.clk_div2p5( clk_80k )
);
// 时钟生成模块  40k, 20k, 10k
clk_div2p5 clk_gen_40k(
	.clk       ( clk_100k ),
	.rstn      ( rst_n   ) ,
	.clk_div2p5( clk_40k )
);
clk_div5 clk_gen_20k(
	.clk       ( clk_100k ),
	.rstn      ( rst_n   ) ,
	.clk_div5  ( clk_20k )
);
clk_div10 clk_gen_10k(
	.clk       ( clk_100k ),
	.rstn      ( rst_n   ) ,
	.clk_div10 ( clk_10k )
);
// 时钟生成模块  8k, 4k, 2k, 1k
clk_div2p5 clk_gen_8k(
	.clk       ( clk_20k ),
	.rstn      ( rst_n   ) ,
	.clk_div2p5( clk_8k )
);
clk_div2p5 clk_gen_4k(
	.clk       ( clk_10k ),
	.rstn      ( rst_n   ) ,
	.clk_div2p5( clk_4k )
);
clk_div5 clk_gen_2k(
	.clk       ( clk_10k ),
	.rstn      ( rst_n   ) ,
	.clk_div5  ( clk_2k )
);
clk_div10 clk_gen_1k(
	.clk       ( clk_10k ),
	.rstn      ( rst_n   ) ,
	.clk_div10 ( clk_1k )
);
// 时钟生成模块  800, 400, 200, 100
clk_div2p5 clk_gen_800(
	.clk       ( clk_2k ),
	.rstn      ( rst_n   ) ,
	.clk_div2p5( clk_800 )
);
clk_div2p5 clk_gen_400(
	.clk       ( clk_1k ),
	.rstn      ( rst_n   ) ,
	.clk_div2p5( clk_400 )
);
clk_div5 clk_gen_200(
	.clk       ( clk_1k ),
	.rstn      ( rst_n   ) ,
	.clk_div5  ( clk_200 )
);
clk_div10 clk_gen_100(
	.clk       ( clk_1k ),
	.rstn      ( rst_n   ) ,
	.clk_div10 ( clk_100 )
);
endmodule

1.3.4 编写 adc_clk_drv.v

根据 寄存器0 slv_reg0，设置ADC时钟

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date: 02/18/2024 02:31:22 PM
// Design Name: 
// Module Name: adc_clk
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//


module adc_clk(
	clk_50m, 
	rst_n, 
	slv_reg0,
	
	adc_clk
    );

input 	wire	clk_50m; 
input 	wire 	rst_n;
input	wire [31:0]	slv_reg0;
output 	wire	adc_clk; 

reg adc_clk_r;
wire	clk_20m;
wire	clk_10m;
wire	clk_8m;
wire	clk_5m;
wire	clk_4m;
wire	clk_2m;
wire	clk_1m;
wire	clk_800k;
wire	clk_400k;
wire	clk_200k;
wire	clk_100k;
wire	clk_80k;
wire	clk_40k;
wire	clk_20k;
wire	clk_10k;
wire	clk_8k;
wire	clk_4k;
wire	clk_2k;
wire	clk_1k;
wire	clk_800;
wire	clk_400;
wire	clk_200;
wire	clk_100;

clk_div clk_gen(
	.clk_50m   (   clk_50m ), 
	.rst_n     (   rst_n   ),
	.clk_20m   (   clk_20m ),
	.clk_10m   (   clk_10m ),
	.clk_8m    (   clk_8m  ),
	.clk_5m    (   clk_5m  ),
	.clk_4m    (   clk_4m  ),
	.clk_2m    (   clk_2m  ),
	.clk_1m    (   clk_1m  ),
	.clk_800k  (   clk_800k),
	.clk_400k  (   clk_400k),
	.clk_200k  (   clk_200k),
	.clk_100k  (   clk_100k),
	.clk_80k   (   clk_80k ),
	.clk_40k   (   clk_40k ),
	.clk_20k   (   clk_20k ),
	.clk_10k   (   clk_10k ),
	.clk_8k    (   clk_8k  ),
	.clk_4k    (   clk_4k  ),
	.clk_2k    (   clk_2k  ),
	.clk_1k    (   clk_1k  ),
	.clk_800   (   clk_800 ),
	.clk_400   (   clk_400 ),
	.clk_200   (   clk_200 ),
	.clk_100   (   clk_100 )
    );


always @( posedge clk_50m or negedge rst_n ) begin
	if( ~rst_n ) begin
		adc_clk_r <= 1'b0;
	end
	else begin
        if ( slv_reg0 >= 32'd20_000_000 ) begin
            adc_clk_r <= clk_20m;
        end
        else if ( slv_reg0 >= 32'd10_000_000 ) begin
            adc_clk_r <= clk_10m;
        end
        else if ( slv_reg0 >= 32'd8_000_000 ) begin
            adc_clk_r <= clk_8m;
        end
        else if ( slv_reg0 >= 32'd5_000_000 ) begin
            adc_clk_r <= clk_5m;
        end
        else if ( slv_reg0 >= 32'd4_000_000 ) begin
            adc_clk_r <= clk_4m;
        end
        else if ( slv_reg0 >= 32'd2_000_000 ) begin
            adc_clk_r <= clk_2m;
        end
        else if ( slv_reg0 >= 32'd1_000_000 ) begin
            adc_clk_r <= clk_1m;
        end
        else if ( slv_reg0 >= 32'd800_000 ) begin
            adc_clk_r <= clk_800k;
        end
        else if ( slv_reg0 >= 32'd400_000 ) begin
            adc_clk_r <= clk_400k;
        end
        else if ( slv_reg0 >= 32'd200_000 ) begin
            adc_clk_r <= clk_200k;
        end
        else if ( slv_reg0 >= 32'd100_000 ) begin
            adc_clk_r <= clk_100k;
        end
        else if ( slv_reg0 >= 32'd80_000 ) begin
            adc_clk_r <= clk_80k;
        end
        else if ( slv_reg0 >= 32'd40_000 ) begin
            adc_clk_r <= clk_40k;
        end
        else if ( slv_reg0 >= 32'd20_000 ) begin
            adc_clk_r <= clk_20k;
        end
        else if ( slv_reg0 >= 32'd10_000 ) begin
            adc_clk_r <= clk_10k;
        end
        else if ( slv_reg0 >= 32'd8_000 ) begin
            adc_clk_r <= clk_8k;
        end
        else if ( slv_reg0 >= 32'd4_000 ) begin
            adc_clk_r <= clk_4k;
        end
        else if ( slv_reg0 >= 32'd2_000 ) begin
            adc_clk_r <= clk_2k;
        end
        else if ( slv_reg0 >= 32'd1_000 ) begin
            adc_clk_r <= clk_1k;
        end
        else if ( slv_reg0 >= 32'd800 ) begin
            adc_clk_r <= clk_800;
        end
        else if ( slv_reg0 >= 32'd400 ) begin
            adc_clk_r <= clk_400;
        end
        else if ( slv_reg0 >= 32'd200 ) begin
            adc_clk_r <= clk_200;
        end
        else if ( slv_reg0 >= 32'd100 ) begin
            adc_clk_r <= clk_100;
        end
        else begin
            adc_clk_r <= clk_1m;
            //adc_clk_r <= 1'b0;
        end
	end
end
//assign adc_clk = adc_clk_r ? 1:0;
assign adc_clk = adc_clk_r;

endmodule

1.3.5 编辑 PS_PL_ADC_8B_v1_0_S00_AXI.v

实现ADC控制的相关逻辑。这里直接放出源码。

`timescale 1 ns / 1 ps

	module PS_PL_ADC_8B_v1_0_S00_AXI #
	(
		// Users to add parameters here

		// User parameters ends
		// Do not modify the parameters beyond this line

		// Width of S_AXI data bus
		parameter integer C_S_AXI_DATA_WIDTH	= 32,
		// Width of S_AXI address bus
		parameter integer C_S_AXI_ADDR_WIDTH	= 10
	)
	(
		// Users to add ports here
        input wire clk_50m,
        output wire adc_clk,
        input wire [7:0] adc_data,
        output  wire adc_pd,

		// User ports ends
		// Do not modify the ports beyond this line

		// Global Clock Signal
		input wire  S_AXI_ACLK,
		// Global Reset Signal. This Signal is Active LOW
		input wire  S_AXI_ARESETN,
		// Write address (issued by master, acceped by Slave)
		input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,
		// Write channel Protection type. This signal indicates the
    		// privilege and security level of the transaction, and whether
    		// the transaction is a data access or an instruction access.
		input wire [2 : 0] S_AXI_AWPROT,
		// Write address valid. This signal indicates that the master signaling
    		// valid write address and control information.
		input wire  S_AXI_AWVALID,
		// Write address ready. This signal indicates that the slave is ready
    		// to accept an address and associated control signals.
		output wire  S_AXI_AWREADY,
		// Write data (issued by master, acceped by Slave) 
		input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,
		// Write strobes. This signal indicates which byte lanes hold
    		// valid data. There is one write strobe bit for each eight
    		// bits of the write data bus.    
		input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,
		// Write valid. This signal indicates that valid write
    		// data and strobes are available.
		input wire  S_AXI_WVALID,
		// Write ready. This signal indicates that the slave
    		// can accept the write data.
		output wire  S_AXI_WREADY,
		// Write response. This signal indicates the status
    		// of the write transaction.
		output wire [1 : 0] S_AXI_BRESP,
		// Write response valid. This signal indicates that the channel
    		// is signaling a valid write response.
		output wire  S_AXI_BVALID,
		// Response ready. This signal indicates that the master
    		// can accept a write response.
		input wire  S_AXI_BREADY,
		// Read address (issued by master, acceped by Slave)
		input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,
		// Protection type. This signal indicates the privilege
    		// and security level of the transaction, and whether the
    		// transaction is a data access or an instruction access.
		input wire [2 : 0] S_AXI_ARPROT,
		// Read address valid. This signal indicates that the channel
    		// is signaling valid read address and control information.
		input wire  S_AXI_ARVALID,
		// Read address ready. This signal indicates that the slave is
    		// ready to accept an address and associated control signals.
		output wire  S_AXI_ARREADY,
		// Read data (issued by slave)
		output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,
		// Read response. This signal indicates the status of the
    		// read transfer.
		output wire [1 : 0] S_AXI_RRESP,
		// Read valid. This signal indicates that the channel is
    		// signaling the required read data.
		output wire  S_AXI_RVALID,
		// Read ready. This signal indicates that the master can
    		// accept the read data and response information.
		input wire  S_AXI_RREADY
	);

	// AXI4LITE signals
	reg [C_S_AXI_ADDR_WIDTH-1 : 0] 	axi_awaddr;
	reg  	axi_awready;
	reg  	axi_wready;
	reg [1 : 0] 	axi_bresp;
	reg  	axi_bvalid;
	reg [C_S_AXI_ADDR_WIDTH-1 : 0] 	axi_araddr;
	reg  	axi_arready;
	reg [C_S_AXI_DATA_WIDTH-1 : 0] 	axi_rdata;
	reg [1 : 0] 	axi_rresp;
	reg  	axi_rvalid;

	// Example-specific design signals
	// local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
	// ADDR_LSB is used for addressing 32/64 bit registers/memories
	// ADDR_LSB = 2 for 32 bits (n downto 2)
	// ADDR_LSB = 3 for 64 bits (n downto 3)
	localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1;
	localparam integer OPT_MEM_ADDR_BITS = 7;
	//----------------------------------------------
	//-- Signals for user logic register space example
	//------------------------------------------------
	//-- Number of Slave Registers 130
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg0;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg1;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg2;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg3;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg4;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg5;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg6;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg7;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg8;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg9;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg10;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg11;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg12;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg13;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg14;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg15;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg16;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg17;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg18;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg19;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg20;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg21;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg22;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg23;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg24;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg25;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg26;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg27;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg28;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg29;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg30;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg31;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg32;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg33;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg34;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg35;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg36;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg37;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg38;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg39;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg40;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg41;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg42;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg43;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg44;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg45;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg46;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg47;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg48;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg49;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg50;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg51;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg52;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg53;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg54;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg55;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg56;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg57;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg58;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg59;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg60;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg61;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg62;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg63;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg64;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg65;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg66;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg67;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg68;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg69;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg70;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg71;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg72;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg73;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg74;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg75;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg76;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg77;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg78;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg79;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg80;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg81;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg82;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg83;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg84;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg85;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg86;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg87;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg88;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg89;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg90;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg91;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg92;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg93;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg94;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg95;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg96;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg97;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg98;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg99;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg100;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg101;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg102;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg103;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg104;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg105;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg106;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg107;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg108;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg109;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg110;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg111;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg112;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg113;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg114;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg115;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg116;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg117;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg118;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg119;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg120;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg121;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg122;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg123;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg124;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg125;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg126;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg127;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg128;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg129;
	wire	 slv_reg_rden;
	wire	 slv_reg_wren;
	reg [C_S_AXI_DATA_WIDTH-1:0]	 reg_data_out;
	integer	 byte_index;
	reg	 aw_en;

	// I/O Connections assignments

	assign S_AXI_AWREADY	= axi_awready;
	assign S_AXI_WREADY	= axi_wready;
	assign S_AXI_BRESP	= axi_bresp;
	assign S_AXI_BVALID	= axi_bvalid;
	assign S_AXI_ARREADY	= axi_arready;
	assign S_AXI_RDATA	= axi_rdata;
	assign S_AXI_RRESP	= axi_rresp;
	assign S_AXI_RVALID	= axi_rvalid;
	// Implement axi_awready generation
	// axi_awready is asserted for one S_AXI_ACLK clock cycle when both
	// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
	// de-asserted when reset is low.

	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_awready <= 1'b0;
	      aw_en <= 1'b1;
	    end 
	  else
	    begin    
	      if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
	        begin
	          // slave is ready to accept write address when 
	          // there is a valid write address and write data
	          // on the write address and data bus. This design 
	          // expects no outstanding transactions. 
	          axi_awready <= 1'b1;
	          aw_en <= 1'b0;
	        end
	        else if (S_AXI_BREADY && axi_bvalid)
	            begin
	              aw_en <= 1'b1;
	              axi_awready <= 1'b0;
	            end
	      else           
	        begin
	          axi_awready <= 1'b0;
	        end
	    end 
	end       

	// Implement axi_awaddr latching
	// This process is used to latch the address when both 
	// S_AXI_AWVALID and S_AXI_WVALID are valid. 

	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_awaddr <= 0;
	    end 
	  else
	    begin    
	      if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
	        begin
	          // Write Address latching 
	          axi_awaddr <= S_AXI_AWADDR;
	        end
	    end 
	end       

	// Implement axi_wready generation
	// axi_wready is asserted for one S_AXI_ACLK clock cycle when both
	// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is 
	// de-asserted when reset is low. 

	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_wready <= 1'b0;
	    end 
	  else
	    begin    
	      if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID && aw_en )
	        begin
	          // slave is ready to accept write data when 
	          // there is a valid write address and write data
	          // on the write address and data bus. This design 
	          // expects no outstanding transactions. 
	          axi_wready <= 1'b1;
	        end
	      else
	        begin
	          axi_wready <= 1'b0;
	        end
	    end 
	end       

	// Implement memory mapped register select and write logic generation
	// The write data is accepted and written to memory mapped registers when
	// axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
	// select byte enables of slave registers while writing.
	// These registers are cleared when reset (active low) is applied.
	// Slave register write enable is asserted when valid address and data are available
	// and the slave is ready to accept the write address and write data.
	assign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID;

	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      slv_reg0 <= 0;
	      slv_reg1 <= 0;
//	      slv_reg2 <= 0;
//	      slv_reg3 <= 0;
//	      slv_reg4 <= 0;
//	      slv_reg5 <= 0;
//	      slv_reg6 <= 0;
//	      slv_reg7 <= 0;
//	      slv_reg8 <= 0;
//	      slv_reg9 <= 0;
//	      slv_reg10 <= 0;
//	      slv_reg11 <= 0;
//	      slv_reg12 <= 0;
//	      slv_reg13 <= 0;
//	      slv_reg14 <= 0;
//	      slv_reg15 <= 0;
//	      slv_reg16 <= 0;
//	      slv_reg17 <= 0;
//	      slv_reg18 <= 0;
//	      slv_reg19 <= 0;
//	      slv_reg20 <= 0;
//	      slv_reg21 <= 0;
//	      slv_reg22 <= 0;
//	      slv_reg23 <= 0;
//	      slv_reg24 <= 0;
//	      slv_reg25 <= 0;
//	      slv_reg26 <= 0;
//	      slv_reg27 <= 0;
//	      slv_reg28 <= 0;
//	      slv_reg29 <= 0;
//	      slv_reg30 <= 0;
//	      slv_reg31 <= 0;
//	      slv_reg32 <= 0;
//	      slv_reg33 <= 0;
//	      slv_reg34 <= 0;
//	      slv_reg35 <= 0;
//	      slv_reg36 <= 0;
//	      slv_reg37 <= 0;
//	      slv_reg38 <= 0;
//	      slv_reg39 <= 0;
//	      slv_reg40 <= 0;
//	      slv_reg41 <= 0;
//	      slv_reg42 <= 0;
//	      slv_reg43 <= 0;
//	      slv_reg44 <= 0;
//	      slv_reg45 <= 0;
//	      slv_reg46 <= 0;
//	      slv_reg47 <= 0;
//	      slv_reg48 <= 0;
//	      slv_reg49 <= 0;
//	      slv_reg50 <= 0;
//	      slv_reg51 <= 0;
//	      slv_reg52 <= 0;
//	      slv_reg53 <= 0;
//	      slv_reg54 <= 0;
//	      slv_reg55 <= 0;
//	      slv_reg56 <= 0;
//	      slv_reg57 <= 0;
//	      slv_reg58 <= 0;
//	      slv_reg59 <= 0;
//	      slv_reg60 <= 0;
//	      slv_reg61 <= 0;
//	      slv_reg62 <= 0;
//	      slv_reg63 <= 0;
//	      slv_reg64 <= 0;
//	      slv_reg65 <= 0;
//	      slv_reg66 <= 0;
//	      slv_reg67 <= 0;
//	      slv_reg68 <= 0;
//	      slv_reg69 <= 0;
//	      slv_reg70 <= 0;
//	      slv_reg71 <= 0;
//	      slv_reg72 <= 0;
//	      slv_reg73 <= 0;
//	      slv_reg74 <= 0;
//	      slv_reg75 <= 0;
//	      slv_reg76 <= 0;
//	      slv_reg77 <= 0;
//	      slv_reg78 <= 0;
//	      slv_reg79 <= 0;
//	      slv_reg80 <= 0;
//	      slv_reg81 <= 0;
//	      slv_reg82 <= 0;
//	      slv_reg83 <= 0;
//	      slv_reg84 <= 0;
//	      slv_reg85 <= 0;
//	      slv_reg86 <= 0;
//	      slv_reg87 <= 0;
//	      slv_reg88 <= 0;
//	      slv_reg89 <= 0;
//	      slv_reg90 <= 0;
//	      slv_reg91 <= 0;
//	      slv_reg92 <= 0;
//	      slv_reg93 <= 0;
//	      slv_reg94 <= 0;
//	      slv_reg95 <= 0;
//	      slv_reg96 <= 0;
//	      slv_reg97 <= 0;
//	      slv_reg98 <= 0;
//	      slv_reg99 <= 0;
//	      slv_reg100 <= 0;
//	      slv_reg101 <= 0;
//	      slv_reg102 <= 0;
//	      slv_reg103 <= 0;
//	      slv_reg104 <= 0;
//	      slv_reg105 <= 0;
//	      slv_reg106 <= 0;
//	      slv_reg107 <= 0;
//	      slv_reg108 <= 0;
//	      slv_reg109 <= 0;
//	      slv_reg110 <= 0;
//	      slv_reg111 <= 0;
//	      slv_reg112 <= 0;
//	      slv_reg113 <= 0;
//	      slv_reg114 <= 0;
//	      slv_reg115 <= 0;
//	      slv_reg116 <= 0;
//	      slv_reg117 <= 0;
//	      slv_reg118 <= 0;
//	      slv_reg119 <= 0;
//	      slv_reg120 <= 0;
//	      slv_reg121 <= 0;
//	      slv_reg122 <= 0;
//	      slv_reg123 <= 0;
//	      slv_reg124 <= 0;
//	      slv_reg125 <= 0;
//	      slv_reg126 <= 0;
//	      slv_reg127 <= 0;
//	      slv_reg128 <= 0;
//	      slv_reg129 <= 0;
	    end 
	  else begin
	    if (slv_reg_wren)
	      begin
	        case ( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
	          8'h00:
	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
	                // Respective byte enables are asserted as per write strobes 
	                // Slave register 0
	                slv_reg0[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
	              end  
	          8'h01:
	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
	                // Respective byte enables are asserted as per write strobes 
	                // Slave register 1
	                slv_reg1[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
	              end  
//	          8'h02:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 2
//	                slv_reg2[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h03:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 3
//	                slv_reg3[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h04:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 4
//	                slv_reg4[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h05:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 5
//	                slv_reg5[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h06:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 6
//	                slv_reg6[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h07:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 7
//	                slv_reg7[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h08:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 8
//	                slv_reg8[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h09:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 9
//	                slv_reg9[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h0A:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 10
//	                slv_reg10[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h0B:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 11
//	                slv_reg11[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h0C:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 12
//	                slv_reg12[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h0D:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 13
//	                slv_reg13[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h0E:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 14
//	                slv_reg14[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h0F:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 15
//	                slv_reg15[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h10:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 16
//	                slv_reg16[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h11:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 17
//	                slv_reg17[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h12:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 18
//	                slv_reg18[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h13:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 19
//	                slv_reg19[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h14:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 20
//	                slv_reg20[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h15:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 21
//	                slv_reg21[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h16:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 22
//	                slv_reg22[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h17:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 23
//	                slv_reg23[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h18:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 24
//	                slv_reg24[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h19:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 25
//	                slv_reg25[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h1A:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 26
//	                slv_reg26[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h1B:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 27
//	                slv_reg27[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h1C:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 28
//	                slv_reg28[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h1D:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 29
//	                slv_reg29[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h1E:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 30
//	                slv_reg30[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h1F:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 31
//	                slv_reg31[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h20:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 32
//	                slv_reg32[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h21:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 33
//	                slv_reg33[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h22:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 34
//	                slv_reg34[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h23:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 35
//	                slv_reg35[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h24:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 36
//	                slv_reg36[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h25:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 37
//	                slv_reg37[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h26:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 38
//	                slv_reg38[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h27:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 39
//	                slv_reg39[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h28:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 40
//	                slv_reg40[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h29:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 41
//	                slv_reg41[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h2A:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 42
//	                slv_reg42[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h2B:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 43
//	                slv_reg43[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h2C:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 44
//	                slv_reg44[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h2D:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 45
//	                slv_reg45[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h2E:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 46
//	                slv_reg46[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h2F:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 47
//	                slv_reg47[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h30:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 48
//	                slv_reg48[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h31:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 49
//	                slv_reg49[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h32:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 50
//	                slv_reg50[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h33:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 51
//	                slv_reg51[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h34:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 52
//	                slv_reg52[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h35:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 53
//	                slv_reg53[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h36:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 54
//	                slv_reg54[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h37:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 55
//	                slv_reg55[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h38:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 56
//	                slv_reg56[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h39:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 57
//	                slv_reg57[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h3A:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 58
//	                slv_reg58[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h3B:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 59
//	                slv_reg59[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h3C:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 60
//	                slv_reg60[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h3D:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 61
//	                slv_reg61[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h3E:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 62
//	                slv_reg62[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h3F:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 63
//	                slv_reg63[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h40:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 64
//	                slv_reg64[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h41:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 65
//	                slv_reg65[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h42:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 66
//	                slv_reg66[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h43:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 67
//	                slv_reg67[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h44:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 68
//	                slv_reg68[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h45:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 69
//	                slv_reg69[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h46:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 70
//	                slv_reg70[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h47:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 71
//	                slv_reg71[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h48:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 72
//	                slv_reg72[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h49:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 73
//	                slv_reg73[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h4A:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 74
//	                slv_reg74[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h4B:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 75
//	                slv_reg75[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h4C:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 76
//	                slv_reg76[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h4D:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 77
//	                slv_reg77[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h4E:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 78
//	                slv_reg78[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h4F:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 79
//	                slv_reg79[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h50:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 80
//	                slv_reg80[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h51:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 81
//	                slv_reg81[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h52:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 82
//	                slv_reg82[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h53:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 83
//	                slv_reg83[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h54:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 84
//	                slv_reg84[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h55:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 85
//	                slv_reg85[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h56:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 86
//	                slv_reg86[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h57:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 87
//	                slv_reg87[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h58:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 88
//	                slv_reg88[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h59:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 89
//	                slv_reg89[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h5A:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 90
//	                slv_reg90[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h5B:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 91
//	                slv_reg91[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h5C:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 92
//	                slv_reg92[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h5D:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 93
//	                slv_reg93[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h5E:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 94
//	                slv_reg94[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h5F:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 95
//	                slv_reg95[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h60:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 96
//	                slv_reg96[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h61:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 97
//	                slv_reg97[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h62:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 98
//	                slv_reg98[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h63:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 99
//	                slv_reg99[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h64:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 100
//	                slv_reg100[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h65:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 101
//	                slv_reg101[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h66:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 102
//	                slv_reg102[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h67:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 103
//	                slv_reg103[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h68:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 104
//	                slv_reg104[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h69:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 105
//	                slv_reg105[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h6A:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 106
//	                slv_reg106[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h6B:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 107
//	                slv_reg107[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h6C:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 108
//	                slv_reg108[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h6D:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 109
//	                slv_reg109[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h6E:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 110
//	                slv_reg110[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h6F:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 111
//	                slv_reg111[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h70:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 112
//	                slv_reg112[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h71:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 113
//	                slv_reg113[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h72:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 114
//	                slv_reg114[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h73:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 115
//	                slv_reg115[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h74:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 116
//	                slv_reg116[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h75:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 117
//	                slv_reg117[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h76:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 118
//	                slv_reg118[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h77:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 119
//	                slv_reg119[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h78:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 120
//	                slv_reg120[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h79:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 121
//	                slv_reg121[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h7A:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 122
//	                slv_reg122[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h7B:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 123
//	                slv_reg123[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h7C:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 124
//	                slv_reg124[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h7D:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 125
//	                slv_reg125[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h7E:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 126
//	                slv_reg126[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h7F:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 127
//	                slv_reg127[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h80:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 128
//	                slv_reg128[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
//	          8'h81:
//	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
//	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//	                // Respective byte enables are asserted as per write strobes 
//	                // Slave register 129
//	                slv_reg129[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
//	              end  
	          default : begin
	                      slv_reg0 <= slv_reg0;
	                      slv_reg1 <= slv_reg1;
//	                      slv_reg2 <= slv_reg2;
//	                      slv_reg3 <= slv_reg3;
//	                      slv_reg4 <= slv_reg4;
//	                      slv_reg5 <= slv_reg5;
//	                      slv_reg6 <= slv_reg6;
//	                      slv_reg7 <= slv_reg7;
//	                      slv_reg8 <= slv_reg8;
//	                      slv_reg9 <= slv_reg9;
//	                      slv_reg10 <= slv_reg10;
//	                      slv_reg11 <= slv_reg11;
//	                      slv_reg12 <= slv_reg12;
//	                      slv_reg13 <= slv_reg13;
//	                      slv_reg14 <= slv_reg14;
//	                      slv_reg15 <= slv_reg15;
//	                      slv_reg16 <= slv_reg16;
//	                      slv_reg17 <= slv_reg17;
//	                      slv_reg18 <= slv_reg18;
//	                      slv_reg19 <= slv_reg19;
//	                      slv_reg20 <= slv_reg20;
//	                      slv_reg21 <= slv_reg21;
//	                      slv_reg22 <= slv_reg22;
//	                      slv_reg23 <= slv_reg23;
//	                      slv_reg24 <= slv_reg24;
//	                      slv_reg25 <= slv_reg25;
//	                      slv_reg26 <= slv_reg26;
//	                      slv_reg27 <= slv_reg27;
//	                      slv_reg28 <= slv_reg28;
//	                      slv_reg29 <= slv_reg29;
//	                      slv_reg30 <= slv_reg30;
//	                      slv_reg31 <= slv_reg31;
//	                      slv_reg32 <= slv_reg32;
//	                      slv_reg33 <= slv_reg33;
//	                      slv_reg34 <= slv_reg34;
//	                      slv_reg35 <= slv_reg35;
//	                      slv_reg36 <= slv_reg36;
//	                      slv_reg37 <= slv_reg37;
//	                      slv_reg38 <= slv_reg38;
//	                      slv_reg39 <= slv_reg39;
//	                      slv_reg40 <= slv_reg40;
//	                      slv_reg41 <= slv_reg41;
//	                      slv_reg42 <= slv_reg42;
//	                      slv_reg43 <= slv_reg43;
//	                      slv_reg44 <= slv_reg44;
//	                      slv_reg45 <= slv_reg45;
//	                      slv_reg46 <= slv_reg46;
//	                      slv_reg47 <= slv_reg47;
//	                      slv_reg48 <= slv_reg48;
//	                      slv_reg49 <= slv_reg49;
//	                      slv_reg50 <= slv_reg50;
//	                      slv_reg51 <= slv_reg51;
//	                      slv_reg52 <= slv_reg52;
//	                      slv_reg53 <= slv_reg53;
//	                      slv_reg54 <= slv_reg54;
//	                      slv_reg55 <= slv_reg55;
//	                      slv_reg56 <= slv_reg56;
//	                      slv_reg57 <= slv_reg57;
//	                      slv_reg58 <= slv_reg58;
//	                      slv_reg59 <= slv_reg59;
//	                      slv_reg60 <= slv_reg60;
//	                      slv_reg61 <= slv_reg61;
//	                      slv_reg62 <= slv_reg62;
//	                      slv_reg63 <= slv_reg63;
//	                      slv_reg64 <= slv_reg64;
//	                      slv_reg65 <= slv_reg65;
//	                      slv_reg66 <= slv_reg66;
//	                      slv_reg67 <= slv_reg67;
//	                      slv_reg68 <= slv_reg68;
//	                      slv_reg69 <= slv_reg69;
//	                      slv_reg70 <= slv_reg70;
//	                      slv_reg71 <= slv_reg71;
//	                      slv_reg72 <= slv_reg72;
//	                      slv_reg73 <= slv_reg73;
//	                      slv_reg74 <= slv_reg74;
//	                      slv_reg75 <= slv_reg75;
//	                      slv_reg76 <= slv_reg76;
//	                      slv_reg77 <= slv_reg77;
//	                      slv_reg78 <= slv_reg78;
//	                      slv_reg79 <= slv_reg79;
//	                      slv_reg80 <= slv_reg80;
//	                      slv_reg81 <= slv_reg81;
//	                      slv_reg82 <= slv_reg82;
//	                      slv_reg83 <= slv_reg83;
//	                      slv_reg84 <= slv_reg84;
//	                      slv_reg85 <= slv_reg85;
//	                      slv_reg86 <= slv_reg86;
//	                      slv_reg87 <= slv_reg87;
//	                      slv_reg88 <= slv_reg88;
//	                      slv_reg89 <= slv_reg89;
//	                      slv_reg90 <= slv_reg90;
//	                      slv_reg91 <= slv_reg91;
//	                      slv_reg92 <= slv_reg92;
//	                      slv_reg93 <= slv_reg93;
//	                      slv_reg94 <= slv_reg94;
//	                      slv_reg95 <= slv_reg95;
//	                      slv_reg96 <= slv_reg96;
//	                      slv_reg97 <= slv_reg97;
//	                      slv_reg98 <= slv_reg98;
//	                      slv_reg99 <= slv_reg99;
//	                      slv_reg100 <= slv_reg100;
//	                      slv_reg101 <= slv_reg101;
//	                      slv_reg102 <= slv_reg102;
//	                      slv_reg103 <= slv_reg103;
//	                      slv_reg104 <= slv_reg104;
//	                      slv_reg105 <= slv_reg105;
//	                      slv_reg106 <= slv_reg106;
//	                      slv_reg107 <= slv_reg107;
//	                      slv_reg108 <= slv_reg108;
//	                      slv_reg109 <= slv_reg109;
//	                      slv_reg110 <= slv_reg110;
//	                      slv_reg111 <= slv_reg111;
//	                      slv_reg112 <= slv_reg112;
//	                      slv_reg113 <= slv_reg113;
//	                      slv_reg114 <= slv_reg114;
//	                      slv_reg115 <= slv_reg115;
//	                      slv_reg116 <= slv_reg116;
//	                      slv_reg117 <= slv_reg117;
//	                      slv_reg118 <= slv_reg118;
//	                      slv_reg119 <= slv_reg119;
//	                      slv_reg120 <= slv_reg120;
//	                      slv_reg121 <= slv_reg121;
//	                      slv_reg122 <= slv_reg122;
//	                      slv_reg123 <= slv_reg123;
//	                      slv_reg124 <= slv_reg124;
//	                      slv_reg125 <= slv_reg125;
//	                      slv_reg126 <= slv_reg126;
//	                      slv_reg127 <= slv_reg127;
//	                      slv_reg128 <= slv_reg128;
//	                      slv_reg129 <= slv_reg129;
	                    end
	        endcase
	      end
	  end
	end    

	// Implement write response logic generation
	// The write response and response valid signals are asserted by the slave 
	// when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.  
	// This marks the acceptance of address and indicates the status of 
	// write transaction.

	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_bvalid  <= 0;
	      axi_bresp   <= 2'b0;
	    end 
	  else
	    begin    
	      if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID)
	        begin
	          // indicates a valid write response is available
	          axi_bvalid <= 1'b1;
	          axi_bresp  <= 2'b0; // 'OKAY' response 
	        end                   // work error responses in future
	      else
	        begin
	          if (S_AXI_BREADY && axi_bvalid) 
	            //check if bready is asserted while bvalid is high) 
	            //(there is a possibility that bready is always asserted high)   
	            begin
	              axi_bvalid <= 1'b0; 
	            end  
	        end
	    end
	end   

	// Implement axi_arready generation
	// axi_arready is asserted for one S_AXI_ACLK clock cycle when
	// S_AXI_ARVALID is asserted. axi_awready is 
	// de-asserted when reset (active low) is asserted. 
	// The read address is also latched when S_AXI_ARVALID is 
	// asserted. axi_araddr is reset to zero on reset assertion.

	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_arready <= 1'b0;
	      axi_araddr  <= 32'b0;
	    end 
	  else
	    begin    
	      if (~axi_arready && S_AXI_ARVALID)
	        begin
	          // indicates that the slave has acceped the valid read address
	          axi_arready <= 1'b1;
	          // Read address latching
	          axi_araddr  <= S_AXI_ARADDR;
	        end
	      else
	        begin
	          axi_arready <= 1'b0;
	        end
	    end 
	end       

	// Implement axi_arvalid generation
	// axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both 
	// S_AXI_ARVALID and axi_arready are asserted. The slave registers 
	// data are available on the axi_rdata bus at this instance. The 
	// assertion of axi_rvalid marks the validity of read data on the 
	// bus and axi_rresp indicates the status of read transaction.axi_rvalid 
	// is deasserted on reset (active low). axi_rresp and axi_rdata are 
	// cleared to zero on reset (active low).  
	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_rvalid <= 0;
	      axi_rresp  <= 0;
	    end 
	  else
	    begin    
	      if (axi_arready && S_AXI_ARVALID && ~axi_rvalid)
	        begin
	          // Valid read data is available at the read data bus
	          axi_rvalid <= 1'b1;
	          axi_rresp  <= 2'b0; // 'OKAY' response
	        end   
	      else if (axi_rvalid && S_AXI_RREADY)
	        begin
	          // Read data is accepted by the master
	          axi_rvalid <= 1'b0;
	        end                
	    end
	end    

	// Implement memory mapped register select and read logic generation
	// Slave register read enable is asserted when valid address is available
	// and the slave is ready to accept the read address.
	assign slv_reg_rden = axi_arready & S_AXI_ARVALID & ~axi_rvalid;
	always @(*)
	begin
	      // Address decoding for reading registers
	      case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
	        8'h00   : reg_data_out <= slv_reg0;
	        8'h01   : reg_data_out <= slv_reg1;
	        8'h02   : reg_data_out <= slv_reg2;
	        8'h03   : reg_data_out <= slv_reg3;
	        8'h04   : reg_data_out <= slv_reg4;
	        8'h05   : reg_data_out <= slv_reg5;
	        8'h06   : reg_data_out <= slv_reg6;
	        8'h07   : reg_data_out <= slv_reg7;
	        8'h08   : reg_data_out <= slv_reg8;
	        8'h09   : reg_data_out <= slv_reg9;
	        8'h0A   : reg_data_out <= slv_reg10;
	        8'h0B   : reg_data_out <= slv_reg11;
	        8'h0C   : reg_data_out <= slv_reg12;
	        8'h0D   : reg_data_out <= slv_reg13;
	        8'h0E   : reg_data_out <= slv_reg14;
	        8'h0F   : reg_data_out <= slv_reg15;
	        8'h10   : reg_data_out <= slv_reg16;
	        8'h11   : reg_data_out <= slv_reg17;
	        8'h12   : reg_data_out <= slv_reg18;
	        8'h13   : reg_data_out <= slv_reg19;
	        8'h14   : reg_data_out <= slv_reg20;
	        8'h15   : reg_data_out <= slv_reg21;
	        8'h16   : reg_data_out <= slv_reg22;
	        8'h17   : reg_data_out <= slv_reg23;
	        8'h18   : reg_data_out <= slv_reg24;
	        8'h19   : reg_data_out <= slv_reg25;
	        8'h1A   : reg_data_out <= slv_reg26;
	        8'h1B   : reg_data_out <= slv_reg27;
	        8'h1C   : reg_data_out <= slv_reg28;
	        8'h1D   : reg_data_out <= slv_reg29;
	        8'h1E   : reg_data_out <= slv_reg30;
	        8'h1F   : reg_data_out <= slv_reg31;
	        8'h20   : reg_data_out <= slv_reg32;
	        8'h21   : reg_data_out <= slv_reg33;
	        8'h22   : reg_data_out <= slv_reg34;
	        8'h23   : reg_data_out <= slv_reg35;
	        8'h24   : reg_data_out <= slv_reg36;
	        8'h25   : reg_data_out <= slv_reg37;
	        8'h26   : reg_data_out <= slv_reg38;
	        8'h27   : reg_data_out <= slv_reg39;
	        8'h28   : reg_data_out <= slv_reg40;
	        8'h29   : reg_data_out <= slv_reg41;
	        8'h2A   : reg_data_out <= slv_reg42;
	        8'h2B   : reg_data_out <= slv_reg43;
	        8'h2C   : reg_data_out <= slv_reg44;
	        8'h2D   : reg_data_out <= slv_reg45;
	        8'h2E   : reg_data_out <= slv_reg46;
	        8'h2F   : reg_data_out <= slv_reg47;
	        8'h30   : reg_data_out <= slv_reg48;
	        8'h31   : reg_data_out <= slv_reg49;
	        8'h32   : reg_data_out <= slv_reg50;
	        8'h33   : reg_data_out <= slv_reg51;
	        8'h34   : reg_data_out <= slv_reg52;
	        8'h35   : reg_data_out <= slv_reg53;
	        8'h36   : reg_data_out <= slv_reg54;
	        8'h37   : reg_data_out <= slv_reg55;
	        8'h38   : reg_data_out <= slv_reg56;
	        8'h39   : reg_data_out <= slv_reg57;
	        8'h3A   : reg_data_out <= slv_reg58;
	        8'h3B   : reg_data_out <= slv_reg59;
	        8'h3C   : reg_data_out <= slv_reg60;
	        8'h3D   : reg_data_out <= slv_reg61;
	        8'h3E   : reg_data_out <= slv_reg62;
	        8'h3F   : reg_data_out <= slv_reg63;
	        8'h40   : reg_data_out <= slv_reg64;
	        8'h41   : reg_data_out <= slv_reg65;
	        8'h42   : reg_data_out <= slv_reg66;
	        8'h43   : reg_data_out <= slv_reg67;
	        8'h44   : reg_data_out <= slv_reg68;
	        8'h45   : reg_data_out <= slv_reg69;
	        8'h46   : reg_data_out <= slv_reg70;
	        8'h47   : reg_data_out <= slv_reg71;
	        8'h48   : reg_data_out <= slv_reg72;
	        8'h49   : reg_data_out <= slv_reg73;
	        8'h4A   : reg_data_out <= slv_reg74;
	        8'h4B   : reg_data_out <= slv_reg75;
	        8'h4C   : reg_data_out <= slv_reg76;
	        8'h4D   : reg_data_out <= slv_reg77;
	        8'h4E   : reg_data_out <= slv_reg78;
	        8'h4F   : reg_data_out <= slv_reg79;
	        8'h50   : reg_data_out <= slv_reg80;
	        8'h51   : reg_data_out <= slv_reg81;
	        8'h52   : reg_data_out <= slv_reg82;
	        8'h53   : reg_data_out <= slv_reg83;
	        8'h54   : reg_data_out <= slv_reg84;
	        8'h55   : reg_data_out <= slv_reg85;
	        8'h56   : reg_data_out <= slv_reg86;
	        8'h57   : reg_data_out <= slv_reg87;
	        8'h58   : reg_data_out <= slv_reg88;
	        8'h59   : reg_data_out <= slv_reg89;
	        8'h5A   : reg_data_out <= slv_reg90;
	        8'h5B   : reg_data_out <= slv_reg91;
	        8'h5C   : reg_data_out <= slv_reg92;
	        8'h5D   : reg_data_out <= slv_reg93;
	        8'h5E   : reg_data_out <= slv_reg94;
	        8'h5F   : reg_data_out <= slv_reg95;
	        8'h60   : reg_data_out <= slv_reg96;
	        8'h61   : reg_data_out <= slv_reg97;
	        8'h62   : reg_data_out <= slv_reg98;
	        8'h63   : reg_data_out <= slv_reg99;
	        8'h64   : reg_data_out <= slv_reg100;
	        8'h65   : reg_data_out <= slv_reg101;
	        8'h66   : reg_data_out <= slv_reg102;
	        8'h67   : reg_data_out <= slv_reg103;
	        8'h68   : reg_data_out <= slv_reg104;
	        8'h69   : reg_data_out <= slv_reg105;
	        8'h6A   : reg_data_out <= slv_reg106;
	        8'h6B   : reg_data_out <= slv_reg107;
	        8'h6C   : reg_data_out <= slv_reg108;
	        8'h6D   : reg_data_out <= slv_reg109;
	        8'h6E   : reg_data_out <= slv_reg110;
	        8'h6F   : reg_data_out <= slv_reg111;
	        8'h70   : reg_data_out <= slv_reg112;
	        8'h71   : reg_data_out <= slv_reg113;
	        8'h72   : reg_data_out <= slv_reg114;
	        8'h73   : reg_data_out <= slv_reg115;
	        8'h74   : reg_data_out <= slv_reg116;
	        8'h75   : reg_data_out <= slv_reg117;
	        8'h76   : reg_data_out <= slv_reg118;
	        8'h77   : reg_data_out <= slv_reg119;
	        8'h78   : reg_data_out <= slv_reg120;
	        8'h79   : reg_data_out <= slv_reg121;
	        8'h7A   : reg_data_out <= slv_reg122;
	        8'h7B   : reg_data_out <= slv_reg123;
	        8'h7C   : reg_data_out <= slv_reg124;
	        8'h7D   : reg_data_out <= slv_reg125;
	        8'h7E   : reg_data_out <= slv_reg126;
	        8'h7F   : reg_data_out <= slv_reg127;
	        8'h80   : reg_data_out <= slv_reg128;
	        8'h81   : reg_data_out <= slv_reg129;
	        default : reg_data_out <= 0;
	      endcase
	end

	// Output register or memory read data
	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_rdata  <= 0;
	    end 
	  else
	    begin    
	      // When there is a valid read address (S_AXI_ARVALID) with 
	      // acceptance of read address by the slave (axi_arready), 
	      // output the read dada 
	      if (slv_reg_rden)
	        begin
	          axi_rdata <= reg_data_out;     // register read data
	        end   
	    end
	end    

	// Add user logic here
    adc_clk adc_clk_drv(
        .clk_50m   (   clk_50m     ), 
        .rst_n     (   1'b1        ), 
        .slv_reg0  (   slv_reg0    ),
        .adc_clk   (   adc_clk     )
        );
        
    reg [15:0] adc_cnt;
    
    always @( posedge adc_clk ) begin
        if ( slv_reg1[31:16] == 16'd1 ) begin
            // idle
            adc_cnt <= 16'd0;
            slv_reg2[31:16] <= slv_reg1[31:16];
            slv_reg2[15:0] <= adc_cnt;
             
              slv_reg3 <= 0;
              slv_reg4 <= 0;
              slv_reg5 <= 0;
              slv_reg6 <= 0;
              slv_reg7 <= 0;
              slv_reg8 <= 0;
              slv_reg9 <= 0;
              slv_reg10 <= 0;
              slv_reg11 <= 0;
              slv_reg12 <= 0;
              slv_reg13 <= 0;
              slv_reg14 <= 0;
              slv_reg15 <= 0;
              slv_reg16 <= 0;
              slv_reg17 <= 0;
              slv_reg18 <= 0;
              slv_reg19 <= 0;
              slv_reg20 <= 0;
              slv_reg21 <= 0;
              slv_reg22 <= 0;
              slv_reg23 <= 0;
              slv_reg24 <= 0;
              slv_reg25 <= 0;
              slv_reg26 <= 0;
              slv_reg27 <= 0;
              slv_reg28 <= 0;
              slv_reg29 <= 0;
              slv_reg30 <= 0;
              slv_reg31 <= 0;
              slv_reg32 <= 0;
              slv_reg33 <= 0;
              slv_reg34 <= 0;
              slv_reg35 <= 0;
              slv_reg36 <= 0;
              slv_reg37 <= 0;
              slv_reg38 <= 0;
              slv_reg39 <= 0;
              slv_reg40 <= 0;
              slv_reg41 <= 0;
              slv_reg42 <= 0;
              slv_reg43 <= 0;
              slv_reg44 <= 0;
              slv_reg45 <= 0;
              slv_reg46 <= 0;
              slv_reg47 <= 0;
              slv_reg48 <= 0;
              slv_reg49 <= 0;
              slv_reg50 <= 0;
              slv_reg51 <= 0;
              slv_reg52 <= 0;
              slv_reg53 <= 0;
              slv_reg54 <= 0;
              slv_reg55 <= 0;
              slv_reg56 <= 0;
              slv_reg57 <= 0;
              slv_reg58 <= 0;
              slv_reg59 <= 0;
              slv_reg60 <= 0;
              slv_reg61 <= 0;
              slv_reg62 <= 0;
              slv_reg63 <= 0;
              slv_reg64 <= 0;
              slv_reg65 <= 0;
              slv_reg66 <= 0;
              slv_reg67 <= 0;
              slv_reg68 <= 0;
              slv_reg69 <= 0;
              slv_reg70 <= 0;
              slv_reg71 <= 0;
              slv_reg72 <= 0;
              slv_reg73 <= 0;
              slv_reg74 <= 0;
              slv_reg75 <= 0;
              slv_reg76 <= 0;
              slv_reg77 <= 0;
              slv_reg78 <= 0;
              slv_reg79 <= 0;
              slv_reg80 <= 0;
              slv_reg81 <= 0;
              slv_reg82 <= 0;
              slv_reg83 <= 0;
              slv_reg84 <= 0;
              slv_reg85 <= 0;
              slv_reg86 <= 0;
              slv_reg87 <= 0;
              slv_reg88 <= 0;
              slv_reg89 <= 0;
              slv_reg90 <= 0;
              slv_reg91 <= 0;
              slv_reg92 <= 0;
              slv_reg93 <= 0;
              slv_reg94 <= 0;
              slv_reg95 <= 0;
              slv_reg96 <= 0;
              slv_reg97 <= 0;
              slv_reg98 <= 0;
              slv_reg99 <= 0;
              slv_reg100 <= 0;
              slv_reg101 <= 0;
              slv_reg102 <= 0;
              slv_reg103 <= 0;
              slv_reg104 <= 0;
              slv_reg105 <= 0;
              slv_reg106 <= 0;
              slv_reg107 <= 0;
              slv_reg108 <= 0;
              slv_reg109 <= 0;
              slv_reg110 <= 0;
              slv_reg111 <= 0;
              slv_reg112 <= 0;
              slv_reg113 <= 0;
              slv_reg114 <= 0;
              slv_reg115 <= 0;
              slv_reg116 <= 0;
              slv_reg117 <= 0;
              slv_reg118 <= 0;
              slv_reg119 <= 0;
              slv_reg120 <= 0;
              slv_reg121 <= 0;
              slv_reg122 <= 0;
              slv_reg123 <= 0;
              slv_reg124 <= 0;
              slv_reg125 <= 0;
              slv_reg126 <= 0;
              slv_reg127 <= 0;
              slv_reg128 <= 0;
              slv_reg129 <= 0;
        end
        else if ( slv_reg1[31:16] == 16'd2 ) begin
            // sample
            if ( adc_cnt >= slv_reg1[15:0]) begin
                // full
                slv_reg2[31:16] <= 16'd4; 
            end
            else begin
                // sampling 
                adc_cnt <= adc_cnt + 1;
                slv_reg2[15:0] <= adc_cnt;
                slv_reg2[31:16] <= 16'd2; 
                
                if( adc_cnt == 16'd0 ) begin slv_reg3[7:0] <= adc_data; end
                else if( adc_cnt == 16'd1 ) begin  slv_reg3[15:8] <= adc_data;  end
                else if( adc_cnt == 16'd2 ) begin slv_reg3[23:16] <= adc_data; end
                else if( adc_cnt == 16'd3 ) begin slv_reg3[31:24] <= adc_data; end
                else if( adc_cnt == 16'd4 ) begin slv_reg4[7:0] <= adc_data; end
                else if( adc_cnt == 16'd5 ) begin slv_reg4[15:8] <= adc_data; end
                else if( adc_cnt == 16'd6 ) begin slv_reg4[23:16] <= adc_data; end
                else if( adc_cnt == 16'd7 ) begin slv_reg4[31:24] <= adc_data; end
                else if( adc_cnt == 16'd8 ) begin slv_reg5[7:0] <= adc_data; end
                else if( adc_cnt == 16'd9 ) begin slv_reg5[15:8] <= adc_data; end
                else if( adc_cnt == 16'd10 ) begin slv_reg5[23:16] <= adc_data; end
                else if( adc_cnt == 16'd11 ) begin slv_reg5[31:24] <= adc_data; end
                else if( adc_cnt == 16'd12 ) begin slv_reg6[7:0] <= adc_data; end
                else if( adc_cnt == 16'd13 ) begin slv_reg6[15:8] <= adc_data; end
                else if( adc_cnt == 16'd14 ) begin slv_reg6[23:16] <= adc_data; end
                else if( adc_cnt == 16'd15 ) begin slv_reg6[31:24] <= adc_data; end
                
                else if( adc_cnt == 16'd16 ) begin slv_reg7[7:0] <= adc_data; end
                else if( adc_cnt == 16'd17 ) begin slv_reg7[15:8] <= adc_data; end
                else if( adc_cnt == 16'd18 ) begin slv_reg7[23:16] <= adc_data; end
                else if( adc_cnt == 16'd19 ) begin slv_reg7[31:24] <= adc_data; end
                else if( adc_cnt == 16'd20 ) begin slv_reg8[7:0] <= adc_data; end
                else if( adc_cnt == 16'd21 ) begin slv_reg8[15:8] <= adc_data; end
                else if( adc_cnt == 16'd22 ) begin slv_reg8[23:16] <= adc_data; end
                else if( adc_cnt == 16'd23 ) begin slv_reg8[31:24] <= adc_data; end
                else if( adc_cnt == 16'd24 ) begin slv_reg9[7:0] <= adc_data; end
                else if( adc_cnt == 16'd25 ) begin slv_reg9[15:8] <= adc_data; end
                else if( adc_cnt == 16'd26 ) begin slv_reg9[23:16] <= adc_data; end
                else if( adc_cnt == 16'd27 ) begin slv_reg9[31:24] <= adc_data; end
                else if( adc_cnt == 16'd28 ) begin slv_reg10[7:0] <= adc_data; end
                else if( adc_cnt == 16'd29 ) begin slv_reg10[15:8] <= adc_data; end
                else if( adc_cnt == 16'd30 ) begin slv_reg10[23:16] <= adc_data; end
                else if( adc_cnt == 16'd31 ) begin slv_reg10[31:24] <= adc_data; end
                else if( adc_cnt == 16'd32 ) begin slv_reg11[7:0] <= adc_data; end
                else if( adc_cnt == 16'd33 ) begin slv_reg11[15:8] <= adc_data; end
                else if( adc_cnt == 16'd34 ) begin slv_reg11[23:16] <= adc_data; end
                else if( adc_cnt == 16'd35 ) begin slv_reg11[31:24] <= adc_data; end
                    
                else if( adc_cnt == 16'd36 ) begin slv_reg12[7:0] <= adc_data; end
                else if( adc_cnt == 16'd37 ) begin slv_reg12[15:8] <= adc_data; end
                else if( adc_cnt == 16'd38 ) begin slv_reg12[23:16] <= adc_data; end
                else if( adc_cnt == 16'd39 ) begin slv_reg12[31:24] <= adc_data; end
                else if( adc_cnt == 16'd40 ) begin slv_reg13[7:0] <= adc_data; end
                else if( adc_cnt == 16'd41 ) begin slv_reg13[15:8] <= adc_data; end
                else if( adc_cnt == 16'd42 ) begin slv_reg13[23:16] <= adc_data; end
                else if( adc_cnt == 16'd43 ) begin slv_reg13[31:24] <= adc_data; end
                else if( adc_cnt == 16'd44 ) begin slv_reg14[7:0] <= adc_data; end
                else if( adc_cnt == 16'd45 ) begin slv_reg14[15:8] <= adc_data; end
                else if( adc_cnt == 16'd46 ) begin slv_reg14[23:16] <= adc_data; end
                else if( adc_cnt == 16'd47 ) begin slv_reg14[31:24] <= adc_data; end
                else if( adc_cnt == 16'd48 ) begin slv_reg15[7:0] <= adc_data; end
                else if( adc_cnt == 16'd49 ) begin slv_reg15[15:8] <= adc_data; end
                else if( adc_cnt == 16'd50 ) begin slv_reg15[23:16] <= adc_data; end
                else if( adc_cnt == 16'd51 ) begin slv_reg15[31:24] <= adc_data; end
                else if( adc_cnt == 16'd52 ) begin slv_reg16[7:0] <= adc_data; end
                else if( adc_cnt == 16'd53 ) begin slv_reg16[15:8] <= adc_data; end
                else if( adc_cnt == 16'd54 ) begin slv_reg16[23:16] <= adc_data; end
                else if( adc_cnt == 16'd55 ) begin slv_reg16[31:24] <= adc_data; end
                else if( adc_cnt == 16'd56 ) begin slv_reg17[7:0] <= adc_data; end
                else if( adc_cnt == 16'd57 ) begin slv_reg17[15:8] <= adc_data; end
                else if( adc_cnt == 16'd58 ) begin slv_reg17[23:16] <= adc_data; end
                else if( adc_cnt == 16'd59 ) begin slv_reg17[31:24] <= adc_data; end
                else if( adc_cnt == 16'd60 ) begin slv_reg18[7:0] <= adc_data; end
                else if( adc_cnt == 16'd61 ) begin slv_reg18[15:8] <= adc_data; end
                else if( adc_cnt == 16'd62 ) begin slv_reg18[23:16] <= adc_data; end
                else if( adc_cnt == 16'd63 ) begin slv_reg18[31:24] <= adc_data; end
                else if( adc_cnt == 16'd64 ) begin slv_reg19[7:0] <= adc_data; end
                else if( adc_cnt == 16'd65 ) begin slv_reg19[15:8] <= adc_data; end
                else if( adc_cnt == 16'd66 ) begin slv_reg19[23:16] <= adc_data; end
                else if( adc_cnt == 16'd67 ) begin slv_reg19[31:24] <= adc_data; end
                else if( adc_cnt == 16'd68 ) begin slv_reg20[7:0] <= adc_data; end
                else if( adc_cnt == 16'd69 ) begin slv_reg20[15:8] <= adc_data; end
                else if( adc_cnt == 16'd70 ) begin slv_reg20[23:16] <= adc_data; end
                else if( adc_cnt == 16'd71 ) begin slv_reg20[31:24] <= adc_data; end
                else if( adc_cnt == 16'd72 ) begin slv_reg21[7:0] <= adc_data; end
                else if( adc_cnt == 16'd73 ) begin slv_reg21[15:8] <= adc_data; end
                else if( adc_cnt == 16'd74 ) begin slv_reg21[23:16] <= adc_data; end
                else if( adc_cnt == 16'd75 ) begin slv_reg21[31:24] <= adc_data; end
                else if( adc_cnt == 16'd76 ) begin slv_reg22[7:0] <= adc_data; end
                else if( adc_cnt == 16'd77 ) begin slv_reg22[15:8] <= adc_data; end
                else if( adc_cnt == 16'd78 ) begin slv_reg22[23:16] <= adc_data; end
                else if( adc_cnt == 16'd79 ) begin slv_reg22[31:24] <= adc_data; end
                else if( adc_cnt == 16'd80 ) begin slv_reg23[7:0] <= adc_data; end
                else if( adc_cnt == 16'd81 ) begin slv_reg23[15:8] <= adc_data; end
                else if( adc_cnt == 16'd82 ) begin slv_reg23[23:16] <= adc_data; end
                else if( adc_cnt == 16'd83 ) begin slv_reg23[31:24] <= adc_data; end
                else if( adc_cnt == 16'd84 ) begin slv_reg24[7:0] <= adc_data; end
                else if( adc_cnt == 16'd85 ) begin slv_reg24[15:8] <= adc_data; end
                else if( adc_cnt == 16'd86 ) begin slv_reg24[23:16] <= adc_data; end
                else if( adc_cnt == 16'd87 ) begin slv_reg24[31:24] <= adc_data; end
                else if( adc_cnt == 16'd88 ) begin slv_reg25[7:0] <= adc_data; end
                else if( adc_cnt == 16'd89 ) begin slv_reg25[15:8] <= adc_data; end
                else if( adc_cnt == 16'd90 ) begin slv_reg25[23:16] <= adc_data; end
                else if( adc_cnt == 16'd91 ) begin slv_reg25[31:24] <= adc_data; end
                else if( adc_cnt == 16'd92 ) begin slv_reg26[7:0] <= adc_data; end
                else if( adc_cnt == 16'd93 ) begin slv_reg26[15:8] <= adc_data; end
                else if( adc_cnt == 16'd94 ) begin slv_reg26[23:16] <= adc_data; end
                else if( adc_cnt == 16'd95 ) begin slv_reg26[31:24] <= adc_data; end
                else if( adc_cnt == 16'd96 ) begin slv_reg27[7:0] <= adc_data; end
                else if( adc_cnt == 16'd97 ) begin slv_reg27[15:8] <= adc_data; end
                else if( adc_cnt == 16'd98 ) begin slv_reg27[23:16] <= adc_data; end
                else if( adc_cnt == 16'd99 ) begin slv_reg27[31:24] <= adc_data; end
                
                else if( adc_cnt == 16'd100 ) begin slv_reg28[7:0] <= adc_data; end
                else if( adc_cnt == 16'd101 ) begin slv_reg28[15:8] <= adc_data; end
                else if( adc_cnt == 16'd102 ) begin slv_reg28[23:16] <= adc_data; end
                else if( adc_cnt == 16'd103 ) begin slv_reg28[31:24] <= adc_data; end
                else if( adc_cnt == 16'd104 ) begin slv_reg29[7:0] <= adc_data; end
                else if( adc_cnt == 16'd105 ) begin slv_reg29[15:8] <= adc_data; end
                else if( adc_cnt == 16'd106 ) begin slv_reg29[23:16] <= adc_data; end
                else if( adc_cnt == 16'd107 ) begin slv_reg29[31:24] <= adc_data; end
                else if( adc_cnt == 16'd108 ) begin slv_reg30[7:0] <= adc_data; end
                else if( adc_cnt == 16'd109 ) begin slv_reg30[15:8] <= adc_data; end
                else if( adc_cnt == 16'd110 ) begin slv_reg30[23:16] <= adc_data; end
                else if( adc_cnt == 16'd111 ) begin slv_reg30[31:24] <= adc_data; end
                else if( adc_cnt == 16'd112 ) begin slv_reg31[7:0] <= adc_data; end
                else if( adc_cnt == 16'd113 ) begin slv_reg31[15:8] <= adc_data; end
                else if( adc_cnt == 16'd114 ) begin slv_reg31[23:16] <= adc_data; end
                else if( adc_cnt == 16'd115 ) begin slv_reg31[31:24] <= adc_data; end
                else if( adc_cnt == 16'd116 ) begin slv_reg32[7:0] <= adc_data; end
                else if( adc_cnt == 16'd117 ) begin slv_reg32[15:8] <= adc_data; end
                else if( adc_cnt == 16'd118 ) begin slv_reg32[23:16] <= adc_data; end
                else if( adc_cnt == 16'd119 ) begin slv_reg32[31:24] <= adc_data; end
                else if( adc_cnt == 16'd120 ) begin slv_reg33[7:0] <= adc_data; end
                else if( adc_cnt == 16'd121 ) begin slv_reg33[15:8] <= adc_data; end
                else if( adc_cnt == 16'd122 ) begin slv_reg33[23:16] <= adc_data; end
                else if( adc_cnt == 16'd123 ) begin slv_reg33[31:24] <= adc_data; end
                else if( adc_cnt == 16'd124 ) begin slv_reg34[7:0] <= adc_data; end
                else if( adc_cnt == 16'd125 ) begin slv_reg34[15:8] <= adc_data; end
                else if( adc_cnt == 16'd126 ) begin slv_reg34[23:16] <= adc_data; end
                else if( adc_cnt == 16'd127 ) begin slv_reg34[31:24] <= adc_data; end
                else if( adc_cnt == 16'd128 ) begin slv_reg35[7:0] <= adc_data; end
                else if( adc_cnt == 16'd129 ) begin slv_reg35[15:8] <= adc_data; end
                else if( adc_cnt == 16'd130 ) begin slv_reg35[23:16] <= adc_data; end
                else if( adc_cnt == 16'd131 ) begin slv_reg35[31:24] <= adc_data; end
                else if( adc_cnt == 16'd132 ) begin slv_reg36[7:0] <= adc_data; end
                else if( adc_cnt == 16'd133 ) begin slv_reg36[15:8] <= adc_data; end
                else if( adc_cnt == 16'd134 ) begin slv_reg36[23:16] <= adc_data; end
                else if( adc_cnt == 16'd135 ) begin slv_reg36[31:24] <= adc_data; end
                else if( adc_cnt == 16'd136 ) begin slv_reg37[7:0] <= adc_data; end
                else if( adc_cnt == 16'd137 ) begin slv_reg37[15:8] <= adc_data; end
                else if( adc_cnt == 16'd138 ) begin slv_reg37[23:16] <= adc_data; end
                else if( adc_cnt == 16'd139 ) begin slv_reg37[31:24] <= adc_data; end
                else if( adc_cnt == 16'd140 ) begin slv_reg38[7:0] <= adc_data; end
                else if( adc_cnt == 16'd141 ) begin slv_reg38[15:8] <= adc_data; end
                else if( adc_cnt == 16'd142 ) begin slv_reg38[23:16] <= adc_data; end
                else if( adc_cnt == 16'd143 ) begin slv_reg38[31:24] <= adc_data; end
                else if( adc_cnt == 16'd144 ) begin slv_reg39[7:0] <= adc_data; end
                else if( adc_cnt == 16'd145 ) begin slv_reg39[15:8] <= adc_data; end
                else if( adc_cnt == 16'd146 ) begin slv_reg39[23:16] <= adc_data; end
                else if( adc_cnt == 16'd147 ) begin slv_reg39[31:24] <= adc_data; end
                else if( adc_cnt == 16'd148 ) begin slv_reg40[7:0] <= adc_data; end
                else if( adc_cnt == 16'd149 ) begin slv_reg40[15:8] <= adc_data; end
                else if( adc_cnt == 16'd150 ) begin slv_reg40[23:16] <= adc_data; end
                else if( adc_cnt == 16'd151 ) begin slv_reg40[31:24] <= adc_data; end
                else if( adc_cnt == 16'd152 ) begin slv_reg41[7:0] <= adc_data; end
                else if( adc_cnt == 16'd153 ) begin slv_reg41[15:8] <= adc_data; end
                else if( adc_cnt == 16'd154 ) begin slv_reg41[23:16] <= adc_data; end
                else if( adc_cnt == 16'd155 ) begin slv_reg41[31:24] <= adc_data; end
                else if( adc_cnt == 16'd156 ) begin slv_reg42[7:0] <= adc_data; end
                else if( adc_cnt == 16'd157 ) begin slv_reg42[15:8] <= adc_data; end
                else if( adc_cnt == 16'd158 ) begin slv_reg42[23:16] <= adc_data; end
                else if( adc_cnt == 16'd159 ) begin slv_reg42[31:24] <= adc_data; end
                else if( adc_cnt == 16'd160 ) begin slv_reg43[7:0] <= adc_data; end
                else if( adc_cnt == 16'd161 ) begin slv_reg43[15:8] <= adc_data; end
                else if( adc_cnt == 16'd162 ) begin slv_reg43[23:16] <= adc_data; end
                else if( adc_cnt == 16'd163 ) begin slv_reg43[31:24] <= adc_data; end
                else if( adc_cnt == 16'd164 ) begin slv_reg44[7:0] <= adc_data; end
                else if( adc_cnt == 16'd165 ) begin slv_reg44[15:8] <= adc_data; end
                else if( adc_cnt == 16'd166 ) begin slv_reg44[23:16] <= adc_data; end
                else if( adc_cnt == 16'd167 ) begin slv_reg44[31:24] <= adc_data; end
                else if( adc_cnt == 16'd168 ) begin slv_reg45[7:0] <= adc_data; end
                else if( adc_cnt == 16'd169 ) begin slv_reg45[15:8] <= adc_data; end
                else if( adc_cnt == 16'd170 ) begin slv_reg45[23:16] <= adc_data; end
                else if( adc_cnt == 16'd171 ) begin slv_reg45[31:24] <= adc_data; end
                else if( adc_cnt == 16'd172 ) begin slv_reg46[7:0] <= adc_data; end
                else if( adc_cnt == 16'd173 ) begin slv_reg46[15:8] <= adc_data; end
                else if( adc_cnt == 16'd174 ) begin slv_reg46[23:16] <= adc_data; end
                else if( adc_cnt == 16'd175 ) begin slv_reg46[31:24] <= adc_data; end
                else if( adc_cnt == 16'd176 ) begin slv_reg47[7:0] <= adc_data; end
                else if( adc_cnt == 16'd177 ) begin slv_reg47[15:8] <= adc_data; end
                else if( adc_cnt == 16'd178 ) begin slv_reg47[23:16] <= adc_data; end
                else if( adc_cnt == 16'd179 ) begin slv_reg47[31:24] <= adc_data; end
                else if( adc_cnt == 16'd180 ) begin slv_reg48[7:0] <= adc_data; end
                else if( adc_cnt == 16'd181 ) begin slv_reg48[15:8] <= adc_data; end
                else if( adc_cnt == 16'd182 ) begin slv_reg48[23:16] <= adc_data; end
                else if( adc_cnt == 16'd183 ) begin slv_reg48[31:24] <= adc_data; end
                else if( adc_cnt == 16'd184 ) begin slv_reg49[7:0] <= adc_data; end
                else if( adc_cnt == 16'd185 ) begin slv_reg49[15:8] <= adc_data; end
                else if( adc_cnt == 16'd186 ) begin slv_reg49[23:16] <= adc_data; end
                else if( adc_cnt == 16'd187 ) begin slv_reg49[31:24] <= adc_data; end
                else if( adc_cnt == 16'd188 ) begin slv_reg50[7:0] <= adc_data; end
                else if( adc_cnt == 16'd189 ) begin slv_reg50[15:8] <= adc_data; end
                else if( adc_cnt == 16'd190 ) begin slv_reg50[23:16] <= adc_data; end
                else if( adc_cnt == 16'd191 ) begin slv_reg50[31:24] <= adc_data; end
                else if( adc_cnt == 16'd192 ) begin slv_reg51[7:0] <= adc_data; end
                else if( adc_cnt == 16'd193 ) begin slv_reg51[15:8] <= adc_data; end
                else if( adc_cnt == 16'd194 ) begin slv_reg51[23:16] <= adc_data; end
                else if( adc_cnt == 16'd195 ) begin slv_reg51[31:24] <= adc_data; end
                else if( adc_cnt == 16'd196 ) begin slv_reg52[7:0] <= adc_data; end
                else if( adc_cnt == 16'd197 ) begin slv_reg52[15:8] <= adc_data; end
                else if( adc_cnt == 16'd198 ) begin slv_reg52[23:16] <= adc_data; end
                else if( adc_cnt == 16'd199 ) begin slv_reg52[31:24] <= adc_data; end
                else if( adc_cnt == 16'd200 ) begin slv_reg53[7:0] <= adc_data; end
                else if( adc_cnt == 16'd201 ) begin slv_reg53[15:8] <= adc_data; end
                else if( adc_cnt == 16'd202 ) begin slv_reg53[23:16] <= adc_data; end
                else if( adc_cnt == 16'd203 ) begin slv_reg53[31:24] <= adc_data; end
                else if( adc_cnt == 16'd204 ) begin slv_reg54[7:0] <= adc_data; end
                else if( adc_cnt == 16'd205 ) begin slv_reg54[15:8] <= adc_data; end
                else if( adc_cnt == 16'd206 ) begin slv_reg54[23:16] <= adc_data; end
                else if( adc_cnt == 16'd207 ) begin slv_reg54[31:24] <= adc_data; end
                else if( adc_cnt == 16'd208 ) begin slv_reg55[7:0] <= adc_data; end
                else if( adc_cnt == 16'd209 ) begin slv_reg55[15:8] <= adc_data; end
                else if( adc_cnt == 16'd210 ) begin slv_reg55[23:16] <= adc_data; end
                else if( adc_cnt == 16'd211 ) begin slv_reg55[31:24] <= adc_data; end
                else if( adc_cnt == 16'd212 ) begin slv_reg56[7:0] <= adc_data; end
                else if( adc_cnt == 16'd213 ) begin slv_reg56[15:8] <= adc_data; end
                else if( adc_cnt == 16'd214 ) begin slv_reg56[23:16] <= adc_data; end
                else if( adc_cnt == 16'd215 ) begin slv_reg56[31:24] <= adc_data; end
                else if( adc_cnt == 16'd216 ) begin slv_reg57[7:0] <= adc_data; end
                else if( adc_cnt == 16'd217 ) begin slv_reg57[15:8] <= adc_data; end
                else if( adc_cnt == 16'd218 ) begin slv_reg57[23:16] <= adc_data; end
                else if( adc_cnt == 16'd219 ) begin slv_reg57[31:24] <= adc_data; end
                else if( adc_cnt == 16'd220 ) begin slv_reg58[7:0] <= adc_data; end
                else if( adc_cnt == 16'd221 ) begin slv_reg58[15:8] <= adc_data; end
                else if( adc_cnt == 16'd222 ) begin slv_reg58[23:16] <= adc_data; end
                else if( adc_cnt == 16'd223 ) begin slv_reg58[31:24] <= adc_data; end
                else if( adc_cnt == 16'd224 ) begin slv_reg59[7:0] <= adc_data; end
                else if( adc_cnt == 16'd225 ) begin slv_reg59[15:8] <= adc_data; end
                else if( adc_cnt == 16'd226 ) begin slv_reg59[23:16] <= adc_data; end
                else if( adc_cnt == 16'd227 ) begin slv_reg59[31:24] <= adc_data; end
                else if( adc_cnt == 16'd228 ) begin slv_reg60[7:0] <= adc_data; end
                else if( adc_cnt == 16'd229 ) begin slv_reg60[15:8] <= adc_data; end
                else if( adc_cnt == 16'd230 ) begin slv_reg60[23:16] <= adc_data; end
                else if( adc_cnt == 16'd231 ) begin slv_reg60[31:24] <= adc_data; end
                else if( adc_cnt == 16'd232 ) begin slv_reg61[7:0] <= adc_data; end
                else if( adc_cnt == 16'd233 ) begin slv_reg61[15:8] <= adc_data; end
                else if( adc_cnt == 16'd234 ) begin slv_reg61[23:16] <= adc_data; end
                else if( adc_cnt == 16'd235 ) begin slv_reg61[31:24] <= adc_data; end
                else if( adc_cnt == 16'd236 ) begin slv_reg62[7:0] <= adc_data; end
                else if( adc_cnt == 16'd237 ) begin slv_reg62[15:8] <= adc_data; end
                else if( adc_cnt == 16'd238 ) begin slv_reg62[23:16] <= adc_data; end
                else if( adc_cnt == 16'd239 ) begin slv_reg62[31:24] <= adc_data; end
                else if( adc_cnt == 16'd240 ) begin slv_reg63[7:0] <= adc_data; end
                else if( adc_cnt == 16'd241 ) begin slv_reg63[15:8] <= adc_data; end
                else if( adc_cnt == 16'd242 ) begin slv_reg63[23:16] <= adc_data; end
                else if( adc_cnt == 16'd243 ) begin slv_reg63[31:24] <= adc_data; end
                else if( adc_cnt == 16'd244 ) begin slv_reg64[7:0] <= adc_data; end
                else if( adc_cnt == 16'd245 ) begin slv_reg64[15:8] <= adc_data; end
                else if( adc_cnt == 16'd246 ) begin slv_reg64[23:16] <= adc_data; end
                else if( adc_cnt == 16'd247 ) begin slv_reg64[31:24] <= adc_data; end
                else if( adc_cnt == 16'd248 ) begin slv_reg65[7:0] <= adc_data; end
                else if( adc_cnt == 16'd249 ) begin slv_reg65[15:8] <= adc_data; end
                else if( adc_cnt == 16'd250 ) begin slv_reg65[23:16] <= adc_data; end
                else if( adc_cnt == 16'd251 ) begin slv_reg65[31:24] <= adc_data; end
                else if( adc_cnt == 16'd252 ) begin slv_reg66[7:0] <= adc_data; end
                else if( adc_cnt == 16'd253 ) begin slv_reg66[15:8] <= adc_data; end
                else if( adc_cnt == 16'd254 ) begin slv_reg66[23:16] <= adc_data; end
                else if( adc_cnt == 16'd255 ) begin slv_reg66[31:24] <= adc_data; end
                else if( adc_cnt == 16'd256 ) begin slv_reg67[7:0] <= adc_data; end
                else if( adc_cnt == 16'd257 ) begin slv_reg67[15:8] <= adc_data; end
                else if( adc_cnt == 16'd258 ) begin slv_reg67[23:16] <= adc_data; end
                else if( adc_cnt == 16'd259 ) begin slv_reg67[31:24] <= adc_data; end
                else if( adc_cnt == 16'd260 ) begin slv_reg68[7:0] <= adc_data; end
                else if( adc_cnt == 16'd261 ) begin slv_reg68[15:8] <= adc_data; end
                else if( adc_cnt == 16'd262 ) begin slv_reg68[23:16] <= adc_data; end
                else if( adc_cnt == 16'd263 ) begin slv_reg68[31:24] <= adc_data; end
                else if( adc_cnt == 16'd264 ) begin slv_reg69[7:0] <= adc_data; end
                else if( adc_cnt == 16'd265 ) begin slv_reg69[15:8] <= adc_data; end
                else if( adc_cnt == 16'd266 ) begin slv_reg69[23:16] <= adc_data; end
                else if( adc_cnt == 16'd267 ) begin slv_reg69[31:24] <= adc_data; end
                else if( adc_cnt == 16'd268 ) begin slv_reg70[7:0] <= adc_data; end
                else if( adc_cnt == 16'd269 ) begin slv_reg70[15:8] <= adc_data; end
                else if( adc_cnt == 16'd270 ) begin slv_reg70[23:16] <= adc_data; end
                else if( adc_cnt == 16'd271 ) begin slv_reg70[31:24] <= adc_data; end
                else if( adc_cnt == 16'd272 ) begin slv_reg71[7:0] <= adc_data; end
                else if( adc_cnt == 16'd273 ) begin slv_reg71[15:8] <= adc_data; end
                else if( adc_cnt == 16'd274 ) begin slv_reg71[23:16] <= adc_data; end
                else if( adc_cnt == 16'd275 ) begin slv_reg71[31:24] <= adc_data; end
                else if( adc_cnt == 16'd276 ) begin slv_reg72[7:0] <= adc_data; end
                else if( adc_cnt == 16'd277 ) begin slv_reg72[15:8] <= adc_data; end
                else if( adc_cnt == 16'd278 ) begin slv_reg72[23:16] <= adc_data; end
                else if( adc_cnt == 16'd279 ) begin slv_reg72[31:24] <= adc_data; end
                else if( adc_cnt == 16'd280 ) begin slv_reg73[7:0] <= adc_data; end
                else if( adc_cnt == 16'd281 ) begin slv_reg73[15:8] <= adc_data; end
                else if( adc_cnt == 16'd282 ) begin slv_reg73[23:16] <= adc_data; end
                else if( adc_cnt == 16'd283 ) begin slv_reg73[31:24] <= adc_data; end
                else if( adc_cnt == 16'd284 ) begin slv_reg74[7:0] <= adc_data; end
                else if( adc_cnt == 16'd285 ) begin slv_reg74[15:8] <= adc_data; end
                else if( adc_cnt == 16'd286 ) begin slv_reg74[23:16] <= adc_data; end
                else if( adc_cnt == 16'd287 ) begin slv_reg74[31:24] <= adc_data; end
                else if( adc_cnt == 16'd288 ) begin slv_reg75[7:0] <= adc_data; end
                else if( adc_cnt == 16'd289 ) begin slv_reg75[15:8] <= adc_data; end
                else if( adc_cnt == 16'd290 ) begin slv_reg75[23:16] <= adc_data; end
                else if( adc_cnt == 16'd291 ) begin slv_reg75[31:24] <= adc_data; end
                else if( adc_cnt == 16'd292 ) begin slv_reg76[7:0] <= adc_data; end
                else if( adc_cnt == 16'd293 ) begin slv_reg76[15:8] <= adc_data; end
                else if( adc_cnt == 16'd294 ) begin slv_reg76[23:16] <= adc_data; end
                else if( adc_cnt == 16'd295 ) begin slv_reg76[31:24] <= adc_data; end
                else if( adc_cnt == 16'd296 ) begin slv_reg77[7:0] <= adc_data; end
                else if( adc_cnt == 16'd297 ) begin slv_reg77[15:8] <= adc_data; end
                else if( adc_cnt == 16'd298 ) begin slv_reg77[23:16] <= adc_data; end
                else if( adc_cnt == 16'd299 ) begin slv_reg77[31:24] <= adc_data; end
                else if( adc_cnt == 16'd300 ) begin slv_reg78[7:0] <= adc_data; end
                else if( adc_cnt == 16'd301 ) begin slv_reg78[15:8] <= adc_data; end
                else if( adc_cnt == 16'd302 ) begin slv_reg78[23:16] <= adc_data; end
                else if( adc_cnt == 16'd303 ) begin slv_reg78[31:24] <= adc_data; end
                else if( adc_cnt == 16'd304 ) begin slv_reg79[7:0] <= adc_data; end
                else if( adc_cnt == 16'd305 ) begin slv_reg79[15:8] <= adc_data; end
                else if( adc_cnt == 16'd306 ) begin slv_reg79[23:16] <= adc_data; end
                else if( adc_cnt == 16'd307 ) begin slv_reg79[31:24] <= adc_data; end
                else if( adc_cnt == 16'd308 ) begin slv_reg80[7:0] <= adc_data; end
                else if( adc_cnt == 16'd309 ) begin slv_reg80[15:8] <= adc_data; end
                else if( adc_cnt == 16'd310 ) begin slv_reg80[23:16] <= adc_data; end
                else if( adc_cnt == 16'd311 ) begin slv_reg80[31:24] <= adc_data; end
                else if( adc_cnt == 16'd312 ) begin slv_reg81[7:0] <= adc_data; end
                else if( adc_cnt == 16'd313 ) begin slv_reg81[15:8] <= adc_data; end
                else if( adc_cnt == 16'd314 ) begin slv_reg81[23:16] <= adc_data; end
                else if( adc_cnt == 16'd315 ) begin slv_reg81[31:24] <= adc_data; end
                else if( adc_cnt == 16'd316 ) begin slv_reg82[7:0] <= adc_data; end
                else if( adc_cnt == 16'd317 ) begin slv_reg82[15:8] <= adc_data; end
                else if( adc_cnt == 16'd318 ) begin slv_reg82[23:16] <= adc_data; end
                else if( adc_cnt == 16'd319 ) begin slv_reg82[31:24] <= adc_data; end
                else if( adc_cnt == 16'd320 ) begin slv_reg83[7:0] <= adc_data; end
                else if( adc_cnt == 16'd321 ) begin slv_reg83[15:8] <= adc_data; end
                else if( adc_cnt == 16'd322 ) begin slv_reg83[23:16] <= adc_data; end
                else if( adc_cnt == 16'd323 ) begin slv_reg83[31:24] <= adc_data; end
                else if( adc_cnt == 16'd324 ) begin slv_reg84[7:0] <= adc_data; end
                else if( adc_cnt == 16'd325 ) begin slv_reg84[15:8] <= adc_data; end
                else if( adc_cnt == 16'd326 ) begin slv_reg84[23:16] <= adc_data; end
                else if( adc_cnt == 16'd327 ) begin slv_reg84[31:24] <= adc_data; end
                else if( adc_cnt == 16'd328 ) begin slv_reg85[7:0] <= adc_data; end
                else if( adc_cnt == 16'd329 ) begin slv_reg85[15:8] <= adc_data; end
                else if( adc_cnt == 16'd330 ) begin slv_reg85[23:16] <= adc_data; end
                else if( adc_cnt == 16'd331 ) begin slv_reg85[31:24] <= adc_data; end
                else if( adc_cnt == 16'd332 ) begin slv_reg86[7:0] <= adc_data; end
                else if( adc_cnt == 16'd333 ) begin slv_reg86[15:8] <= adc_data; end
                else if( adc_cnt == 16'd334 ) begin slv_reg86[23:16] <= adc_data; end
                else if( adc_cnt == 16'd335 ) begin slv_reg86[31:24] <= adc_data; end
                else if( adc_cnt == 16'd336 ) begin slv_reg87[7:0] <= adc_data; end
                else if( adc_cnt == 16'd337 ) begin slv_reg87[15:8] <= adc_data; end
                else if( adc_cnt == 16'd338 ) begin slv_reg87[23:16] <= adc_data; end
                else if( adc_cnt == 16'd339 ) begin slv_reg87[31:24] <= adc_data; end
                else if( adc_cnt == 16'd340 ) begin slv_reg88[7:0] <= adc_data; end
                else if( adc_cnt == 16'd341 ) begin slv_reg88[15:8] <= adc_data; end
                else if( adc_cnt == 16'd342 ) begin slv_reg88[23:16] <= adc_data; end
                else if( adc_cnt == 16'd343 ) begin slv_reg88[31:24] <= adc_data; end
                else if( adc_cnt == 16'd344 ) begin slv_reg89[7:0] <= adc_data; end
                else if( adc_cnt == 16'd345 ) begin slv_reg89[15:8] <= adc_data; end
                else if( adc_cnt == 16'd346 ) begin slv_reg89[23:16] <= adc_data; end
                else if( adc_cnt == 16'd347 ) begin slv_reg89[31:24] <= adc_data; end
                else if( adc_cnt == 16'd348 ) begin slv_reg90[7:0] <= adc_data; end
                else if( adc_cnt == 16'd349 ) begin slv_reg90[15:8] <= adc_data; end
                else if( adc_cnt == 16'd350 ) begin slv_reg90[23:16] <= adc_data; end
                else if( adc_cnt == 16'd351 ) begin slv_reg90[31:24] <= adc_data; end
                else if( adc_cnt == 16'd352 ) begin slv_reg91[7:0] <= adc_data; end
                else if( adc_cnt == 16'd353 ) begin slv_reg91[15:8] <= adc_data; end
                else if( adc_cnt == 16'd354 ) begin slv_reg91[23:16] <= adc_data; end
                else if( adc_cnt == 16'd355 ) begin slv_reg91[31:24] <= adc_data; end
                else if( adc_cnt == 16'd356 ) begin slv_reg92[7:0] <= adc_data; end
                else if( adc_cnt == 16'd357 ) begin slv_reg92[15:8] <= adc_data; end
                else if( adc_cnt == 16'd358 ) begin slv_reg92[23:16] <= adc_data; end
                else if( adc_cnt == 16'd359 ) begin slv_reg92[31:24] <= adc_data; end
                else if( adc_cnt == 16'd360 ) begin slv_reg93[7:0] <= adc_data; end
                else if( adc_cnt == 16'd361 ) begin slv_reg93[15:8] <= adc_data; end
                else if( adc_cnt == 16'd362 ) begin slv_reg93[23:16] <= adc_data; end
                else if( adc_cnt == 16'd363 ) begin slv_reg93[31:24] <= adc_data; end
                else if( adc_cnt == 16'd364 ) begin slv_reg94[7:0] <= adc_data; end
                else if( adc_cnt == 16'd365 ) begin slv_reg94[15:8] <= adc_data; end
                else if( adc_cnt == 16'd366 ) begin slv_reg94[23:16] <= adc_data; end
                else if( adc_cnt == 16'd367 ) begin slv_reg94[31:24] <= adc_data; end
                else if( adc_cnt == 16'd368 ) begin slv_reg95[7:0] <= adc_data; end
                else if( adc_cnt == 16'd369 ) begin slv_reg95[15:8] <= adc_data; end
                else if( adc_cnt == 16'd370 ) begin slv_reg95[23:16] <= adc_data; end
                else if( adc_cnt == 16'd371 ) begin slv_reg95[31:24] <= adc_data; end
                else if( adc_cnt == 16'd372 ) begin slv_reg96[7:0] <= adc_data; end
                else if( adc_cnt == 16'd373 ) begin slv_reg96[15:8] <= adc_data; end
                else if( adc_cnt == 16'd374 ) begin slv_reg96[23:16] <= adc_data; end
                else if( adc_cnt == 16'd375 ) begin slv_reg96[31:24] <= adc_data; end
                else if( adc_cnt == 16'd376 ) begin slv_reg97[7:0] <= adc_data; end
                else if( adc_cnt == 16'd377 ) begin slv_reg97[15:8] <= adc_data; end
                else if( adc_cnt == 16'd378 ) begin slv_reg97[23:16] <= adc_data; end
                else if( adc_cnt == 16'd379 ) begin slv_reg97[31:24] <= adc_data; end
                else if( adc_cnt == 16'd380 ) begin slv_reg98[7:0] <= adc_data; end
                else if( adc_cnt == 16'd381 ) begin slv_reg98[15:8] <= adc_data; end
                else if( adc_cnt == 16'd382 ) begin slv_reg98[23:16] <= adc_data; end
                else if( adc_cnt == 16'd383 ) begin slv_reg98[31:24] <= adc_data; end
                else if( adc_cnt == 16'd384 ) begin slv_reg99[7:0] <= adc_data; end
                else if( adc_cnt == 16'd385 ) begin slv_reg99[15:8] <= adc_data; end
                else if( adc_cnt == 16'd386 ) begin slv_reg99[23:16] <= adc_data; end
                else if( adc_cnt == 16'd387 ) begin slv_reg99[31:24] <= adc_data; end
                
                else if( adc_cnt == 16'd388 ) begin slv_reg100[7:0] <= adc_data; end
                else if( adc_cnt == 16'd389 ) begin slv_reg100[15:8] <= adc_data; end
                else if( adc_cnt == 16'd390 ) begin slv_reg100[23:16] <= adc_data; end
                else if( adc_cnt == 16'd391 ) begin slv_reg100[31:24] <= adc_data; end
                else if( adc_cnt == 16'd392 ) begin slv_reg101[7:0] <= adc_data; end
                else if( adc_cnt == 16'd393 ) begin slv_reg101[15:8] <= adc_data; end
                else if( adc_cnt == 16'd394 ) begin slv_reg101[23:16] <= adc_data; end
                else if( adc_cnt == 16'd395 ) begin slv_reg101[31:24] <= adc_data; end
                else if( adc_cnt == 16'd396 ) begin slv_reg102[7:0] <= adc_data; end
                else if( adc_cnt == 16'd397 ) begin slv_reg102[15:8] <= adc_data; end
                else if( adc_cnt == 16'd398 ) begin slv_reg102[23:16] <= adc_data; end
                else if( adc_cnt == 16'd399 ) begin slv_reg102[31:24] <= adc_data; end
                else if( adc_cnt == 16'd400 ) begin slv_reg103[7:0] <= adc_data; end
                else if( adc_cnt == 16'd401 ) begin slv_reg103[15:8] <= adc_data; end
                else if( adc_cnt == 16'd402 ) begin slv_reg103[23:16] <= adc_data; end
                else if( adc_cnt == 16'd403 ) begin slv_reg103[31:24] <= adc_data; end
                else if( adc_cnt == 16'd404 ) begin slv_reg104[7:0] <= adc_data; end
                else if( adc_cnt == 16'd405 ) begin slv_reg104[15:8] <= adc_data; end
                else if( adc_cnt == 16'd406 ) begin slv_reg104[23:16] <= adc_data; end
                else if( adc_cnt == 16'd407 ) begin slv_reg104[31:24] <= adc_data; end
                else if( adc_cnt == 16'd408 ) begin slv_reg105[7:0] <= adc_data; end
                else if( adc_cnt == 16'd409 ) begin slv_reg105[15:8] <= adc_data; end
                else if( adc_cnt == 16'd410 ) begin slv_reg105[23:16] <= adc_data; end
                else if( adc_cnt == 16'd411 ) begin slv_reg105[31:24] <= adc_data; end
                else if( adc_cnt == 16'd412 ) begin slv_reg106[7:0] <= adc_data; end
                else if( adc_cnt == 16'd413 ) begin slv_reg106[15:8] <= adc_data; end
                else if( adc_cnt == 16'd414 ) begin slv_reg106[23:16] <= adc_data; end
                else if( adc_cnt == 16'd415 ) begin slv_reg106[31:24] <= adc_data; end
                else if( adc_cnt == 16'd416 ) begin slv_reg107[7:0] <= adc_data; end
                else if( adc_cnt == 16'd417 ) begin slv_reg107[15:8] <= adc_data; end
                else if( adc_cnt == 16'd418 ) begin slv_reg107[23:16] <= adc_data; end
                else if( adc_cnt == 16'd419 ) begin slv_reg107[31:24] <= adc_data; end
                else if( adc_cnt == 16'd420 ) begin slv_reg108[7:0] <= adc_data; end
                else if( adc_cnt == 16'd421 ) begin slv_reg108[15:8] <= adc_data; end
                else if( adc_cnt == 16'd422 ) begin slv_reg108[23:16] <= adc_data; end
                else if( adc_cnt == 16'd423 ) begin slv_reg108[31:24] <= adc_data; end
                else if( adc_cnt == 16'd424 ) begin slv_reg109[7:0] <= adc_data; end
                else if( adc_cnt == 16'd425 ) begin slv_reg109[15:8] <= adc_data; end
                else if( adc_cnt == 16'd426 ) begin slv_reg109[23:16] <= adc_data; end
                else if( adc_cnt == 16'd427 ) begin slv_reg109[31:24] <= adc_data; end
                else if( adc_cnt == 16'd428 ) begin slv_reg110[7:0] <= adc_data; end
                else if( adc_cnt == 16'd429 ) begin slv_reg110[15:8] <= adc_data; end
                else if( adc_cnt == 16'd430 ) begin slv_reg110[23:16] <= adc_data; end
                else if( adc_cnt == 16'd431 ) begin slv_reg110[31:24] <= adc_data; end
                else if( adc_cnt == 16'd432 ) begin slv_reg111[7:0] <= adc_data; end
                else if( adc_cnt == 16'd433 ) begin slv_reg111[15:8] <= adc_data; end
                else if( adc_cnt == 16'd434 ) begin slv_reg111[23:16] <= adc_data; end
                else if( adc_cnt == 16'd435 ) begin slv_reg111[31:24] <= adc_data; end
                else if( adc_cnt == 16'd436 ) begin slv_reg112[7:0] <= adc_data; end
                else if( adc_cnt == 16'd437 ) begin slv_reg112[15:8] <= adc_data; end
                else if( adc_cnt == 16'd438 ) begin slv_reg112[23:16] <= adc_data; end
                else if( adc_cnt == 16'd439 ) begin slv_reg112[31:24] <= adc_data; end
                else if( adc_cnt == 16'd440 ) begin slv_reg113[7:0] <= adc_data; end
                else if( adc_cnt == 16'd441 ) begin slv_reg113[15:8] <= adc_data; end
                else if( adc_cnt == 16'd442 ) begin slv_reg113[23:16] <= adc_data; end
                else if( adc_cnt == 16'd443 ) begin slv_reg113[31:24] <= adc_data; end
                else if( adc_cnt == 16'd444 ) begin slv_reg114[7:0] <= adc_data; end
                else if( adc_cnt == 16'd445 ) begin slv_reg114[15:8] <= adc_data; end
                else if( adc_cnt == 16'd446 ) begin slv_reg114[23:16] <= adc_data; end
                else if( adc_cnt == 16'd447 ) begin slv_reg114[31:24] <= adc_data; end
                else if( adc_cnt == 16'd448 ) begin slv_reg115[7:0] <= adc_data; end
                else if( adc_cnt == 16'd449 ) begin slv_reg115[15:8] <= adc_data; end
                else if( adc_cnt == 16'd450 ) begin slv_reg115[23:16] <= adc_data; end
                else if( adc_cnt == 16'd451 ) begin slv_reg115[31:24] <= adc_data; end
                else if( adc_cnt == 16'd452 ) begin slv_reg116[7:0] <= adc_data; end
                else if( adc_cnt == 16'd453 ) begin slv_reg116[15:8] <= adc_data; end
                else if( adc_cnt == 16'd454 ) begin slv_reg116[23:16] <= adc_data; end
                else if( adc_cnt == 16'd455 ) begin slv_reg116[31:24] <= adc_data; end
                else if( adc_cnt == 16'd456 ) begin slv_reg117[7:0] <= adc_data; end
                else if( adc_cnt == 16'd457 ) begin slv_reg117[15:8] <= adc_data; end
                else if( adc_cnt == 16'd458 ) begin slv_reg117[23:16] <= adc_data; end
                else if( adc_cnt == 16'd459 ) begin slv_reg117[31:24] <= adc_data; end
                else if( adc_cnt == 16'd460 ) begin slv_reg118[7:0] <= adc_data; end
                else if( adc_cnt == 16'd461 ) begin slv_reg118[15:8] <= adc_data; end
                else if( adc_cnt == 16'd462 ) begin slv_reg118[23:16] <= adc_data; end
                else if( adc_cnt == 16'd463 ) begin slv_reg118[31:24] <= adc_data; end
                else if( adc_cnt == 16'd464 ) begin slv_reg119[7:0] <= adc_data; end
                else if( adc_cnt == 16'd465 ) begin slv_reg119[15:8] <= adc_data; end
                else if( adc_cnt == 16'd466 ) begin slv_reg119[23:16] <= adc_data; end
                else if( adc_cnt == 16'd467 ) begin slv_reg119[31:24] <= adc_data; end
                else if( adc_cnt == 16'd468 ) begin slv_reg120[7:0] <= adc_data; end
                else if( adc_cnt == 16'd469 ) begin slv_reg120[15:8] <= adc_data; end
                else if( adc_cnt == 16'd470 ) begin slv_reg120[23:16] <= adc_data; end
                else if( adc_cnt == 16'd471 ) begin slv_reg120[31:24] <= adc_data; end
                else if( adc_cnt == 16'd472 ) begin slv_reg121[7:0] <= adc_data; end
                else if( adc_cnt == 16'd473 ) begin slv_reg121[15:8] <= adc_data; end
                else if( adc_cnt == 16'd474 ) begin slv_reg121[23:16] <= adc_data; end
                else if( adc_cnt == 16'd475 ) begin slv_reg121[31:24] <= adc_data; end
                else if( adc_cnt == 16'd476 ) begin slv_reg122[7:0] <= adc_data; end
                else if( adc_cnt == 16'd477 ) begin slv_reg122[15:8] <= adc_data; end
                else if( adc_cnt == 16'd478 ) begin slv_reg122[23:16] <= adc_data; end
                else if( adc_cnt == 16'd479 ) begin slv_reg122[31:24] <= adc_data; end
                else if( adc_cnt == 16'd480 ) begin slv_reg123[7:0] <= adc_data; end
                else if( adc_cnt == 16'd481 ) begin slv_reg123[15:8] <= adc_data; end
                else if( adc_cnt == 16'd482 ) begin slv_reg123[23:16] <= adc_data; end
                else if( adc_cnt == 16'd483 ) begin slv_reg123[31:24] <= adc_data; end
                else if( adc_cnt == 16'd484 ) begin slv_reg124[7:0] <= adc_data; end
                else if( adc_cnt == 16'd485 ) begin slv_reg124[15:8] <= adc_data; end
                else if( adc_cnt == 16'd486 ) begin slv_reg124[23:16] <= adc_data; end
                else if( adc_cnt == 16'd487 ) begin slv_reg124[31:24] <= adc_data; end
                else if( adc_cnt == 16'd488 ) begin slv_reg125[7:0] <= adc_data; end
                else if( adc_cnt == 16'd489 ) begin slv_reg125[15:8] <= adc_data; end
                else if( adc_cnt == 16'd490 ) begin slv_reg125[23:16] <= adc_data; end
                else if( adc_cnt == 16'd491 ) begin slv_reg125[31:24] <= adc_data; end
                else if( adc_cnt == 16'd492 ) begin slv_reg126[7:0] <= adc_data; end
                else if( adc_cnt == 16'd493 ) begin slv_reg126[15:8] <= adc_data; end
                else if( adc_cnt == 16'd494 ) begin slv_reg126[23:16] <= adc_data; end
                else if( adc_cnt == 16'd495 ) begin slv_reg126[31:24] <= adc_data; end
                else if( adc_cnt == 16'd496 ) begin slv_reg127[7:0] <= adc_data; end
                else if( adc_cnt == 16'd497 ) begin slv_reg127[15:8] <= adc_data; end
                else if( adc_cnt == 16'd498 ) begin slv_reg127[23:16] <= adc_data; end
                else if( adc_cnt == 16'd499 ) begin slv_reg127[31:24] <= adc_data; end
                else if( adc_cnt == 16'd500 ) begin slv_reg128[7:0] <= adc_data; end
                else if( adc_cnt == 16'd501 ) begin slv_reg128[15:8] <= adc_data; end
                else if( adc_cnt == 16'd502 ) begin slv_reg128[23:16] <= adc_data; end
                else if( adc_cnt == 16'd503 ) begin slv_reg128[31:24] <= adc_data; end
                else if( adc_cnt == 16'd504 ) begin slv_reg129[7:0] <= adc_data; end
                else if( adc_cnt == 16'd505 ) begin slv_reg129[15:8] <= adc_data; end
            end
        end
        else begin
            slv_reg2[31:16] <= slv_reg1[31:16];
            adc_cnt <= 16'd0;
            slv_reg2[15:0] <= adc_cnt;
        end
    end

    assign adc_pd = 1'b0;



	// User logic ends

	endmodule

1.3.6 打包

PROJECT MANAGER -> Edit Package IP - PS_PL_ADC_8B -> 
    -> File Groups -> Merge changes from File Groups Wizard
    -> Customization Parameters -> Merge changes from File Groups Wizard
    -> Review and Package -> Re-Package IP

1.4 创建一个block

1.4.1 zynq + hdmi 

这里创建block按照 hdmi显示的过程进行。便于后续开发界面程序。

petalinux2018 zynq7 hdmi显示-CSDN博客https://blog.csdn.net/qq_27158179/article/details/136232621

1.4.2 PS_PL_ADC_8B(ch1)

Diagram -> + -> PS_PL_ADC_8B_v1.0 -> OK
Run Connection Automation -> 勾选 All Automation -> OK

    
点击 PS_PL_ADC_8B_0 的 adc_clk -> 右键 -> Create Port -> 
    -> Port name:    ad_clk_ch1
    -> Direction:    Output
    -> Type:        Clock
-> OK

点击 PS_PL_ADC_8B_0 的 adc_pd -> 右键 -> Create Port -> 
    -> Port name:    ad_pd_ch1
    -> Direction:    output
    -> Type:        Other
-> OK

点击 PS_PL_ADC_8B_0 的 adc_data -> 右键 -> Create Port -> 
    -> Port name:    ad_data_ch1
    -> Direction:    Input
    -> Type:        Other
-> OK

1.4.3 PS_PL_DAC_8B(ch1)

Diagram -> + -> PS_PL_DAC_8B_v1_0 -> OK
Run Connection Automation -> 勾选 All Automation -> OK

点击 PS_PL_DAC_8B_0 的 dac_clk -> 右键 -> Create Port -> 
    -> Port name:    da_clk_ch1
    -> Direction:    Output
    -> Type:        Clock
-> OK

点击 PS_PL_DAC_8B_0 的 dac_data -> 右键 -> Create Port -> 
    -> Port name:    da_data_ch1
    -> Direction:    Input
    -> Type:        Data
-> OK

点击 PS_PL_DAC_8B_0 的 adc_pd -> 右键 -> Create Port -> 
    -> Port name:    da_pd_ch1
    -> Direction:    output
    -> Type:        Other
-> OK

点击 PS_PL_DAC_8B_0 的 clk_50m -> 右键 -> Create Port -> 
    -> Port name:    clk_50m
    -> Direction:    input
    -> Type:        Other
-> OK

1.4.4 ad和da的50Mhz时钟

连线
连接 端口 clk_50m 到 PS_PL_ADC_8B_0 的 clk_50m
连接 端口 clk_50m 到 PS_PL_DAC_8B_0 的 clk_50m
 

1.4.5 block diagram截图

只有zynq和hdmi:

只有zynq和adc dac：

 zynq + hdmi + adc dac:

1.5 create HDL wrapper

source -> Design Source -> 右键 ZYNQ_CORE -> create HDL wrapper -> OK

1.6 引脚约束

添加约束文件，内容linux_sd_adda.xdc：

得到了 Sources -> Constrants -> constrs_1 -> linux_sd_adda.xdc

set_property PACKAGE_PIN H16 [get_ports clk_50m]
set_property IOSTANDARD LVCMOS33 [get_ports clk_50m]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_50m_IBUF]

set_property PACKAGE_PIN K17 [get_ports TMDS_0_clk_p]
set_property PACKAGE_PIN G19 [get_ports {TMDS_0_data_p[0]}]
set_property PACKAGE_PIN F19 [get_ports {TMDS_0_data_p[1]}]
set_property PACKAGE_PIN D19 [get_ports {TMDS_0_data_p[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {HDMI_OEN[0]}]
set_property PACKAGE_PIN M20 [get_ports {HDMI_OEN[0]}]

set_property IOSTANDARD LVCMOS33 [get_ports {GPIO_0_tri_io[*]}]
set_property PACKAGE_PIN B19 [get_ports {GPIO_0_tri_io[7]}]
set_property PACKAGE_PIN J15 [get_ports {GPIO_0_tri_io[6]}]
set_property PACKAGE_PIN H17 [get_ports {GPIO_0_tri_io[5]}]
set_property PACKAGE_PIN B20 [get_ports {GPIO_0_tri_io[4]}]
set_property PACKAGE_PIN T19 [get_ports {GPIO_0_tri_io[3]}]
set_property PACKAGE_PIN R19 [get_ports {GPIO_0_tri_io[2]}]
set_property PACKAGE_PIN C20 [get_ports {GPIO_0_tri_io[1]}]
set_property PACKAGE_PIN G14 [get_ports {GPIO_0_tri_io[0]}]

set_property PACKAGE_PIN R18 [get_ports {da_data_ch1[0]}]
set_property PACKAGE_PIN T17 [get_ports {da_data_ch1[1]}]
set_property PACKAGE_PIN P20 [get_ports {da_data_ch1[2]}]
set_property PACKAGE_PIN N20 [get_ports {da_data_ch1[3]}]
set_property PACKAGE_PIN P18 [get_ports {da_data_ch1[4]}]
set_property PACKAGE_PIN N17 [get_ports {da_data_ch1[5]}]
set_property PACKAGE_PIN P19 [get_ports {da_data_ch1[6]}]
set_property PACKAGE_PIN N18 [get_ports {da_data_ch1[7]}]

set_property IOSTANDARD LVCMOS33 [get_ports {da_data_ch1[*]}]
set_property IOSTANDARD LVCMOS33 [get_ports {da_data_ch2[*]}]

set_property PACKAGE_PIN U12 [get_ports {ad_data_ch1[0]}]
set_property PACKAGE_PIN T12 [get_ports {ad_data_ch1[1]}]
set_property PACKAGE_PIN W13 [get_ports {ad_data_ch1[2]}]
set_property PACKAGE_PIN V12 [get_ports {ad_data_ch1[3]}]
set_property PACKAGE_PIN V13 [get_ports {ad_data_ch1[4]}]
set_property PACKAGE_PIN U13 [get_ports {ad_data_ch1[5]}]
set_property PACKAGE_PIN U15 [get_ports {ad_data_ch1[6]}]
set_property PACKAGE_PIN U14 [get_ports {ad_data_ch1[7]}]

set_property IOSTANDARD LVCMOS33 [get_ports {ad_data_ch1[*]}]
set_property IOSTANDARD LVCMOS33 [get_ports {ad_data_ch2[*]}]

set_property PACKAGE_PIN T10 [get_ports ad_clk_ch1]
set_property PACKAGE_PIN T20 [get_ports da_clk_ch1]
set_property PACKAGE_PIN T11 [get_ports ad_pd_ch1]

set_property IOSTANDARD LVCMOS33 [get_ports ad_clk_ch1]
set_property IOSTANDARD LVCMOS33 [get_ports da_clk_ch1]
set_property IOSTANDARD LVCMOS33 [get_ports ad_pd_ch1]

set_property IOSTANDARD LVCMOS33 [get_ports ad_clk_ch2]
set_property IOSTANDARD LVCMOS33 [get_ports da_clk_ch2]
set_property IOSTANDARD LVCMOS33 [get_ports ad_pd_ch2]

set_property PACKAGE_PIN R16 [get_ports {ad_data_ch2[7]}]
set_property PACKAGE_PIN R17 [get_ports {ad_data_ch2[6]}]
set_property PACKAGE_PIN V17 [get_ports {ad_data_ch2[5]}]
set_property PACKAGE_PIN V18 [get_ports {ad_data_ch2[4]}]
set_property PACKAGE_PIN T16 [get_ports {ad_data_ch2[3]}]
set_property PACKAGE_PIN U17 [get_ports {ad_data_ch2[2]}]
set_property PACKAGE_PIN T14 [get_ports {ad_data_ch2[1]}]
set_property PACKAGE_PIN T15 [get_ports {ad_data_ch2[0]}]
set_property PACKAGE_PIN R14 [get_ports ad_clk_ch2]
set_property PACKAGE_PIN P14 [get_ports ad_pd_ch2]
set_property PACKAGE_PIN J18 [get_ports {da_data_ch2[7]}]
set_property PACKAGE_PIN H18 [get_ports {da_data_ch2[6]}]
set_property PACKAGE_PIN G17 [get_ports {da_data_ch2[5]}]
set_property PACKAGE_PIN G18 [get_ports {da_data_ch2[4]}]
set_property PACKAGE_PIN K14 [get_ports {da_data_ch2[3]}]
set_property PACKAGE_PIN J14 [get_ports {da_data_ch2[2]}]
set_property PACKAGE_PIN H15 [get_ports {da_data_ch2[1]}]
set_property PACKAGE_PIN G15 [get_ports {da_data_ch2[0]}]
set_property PACKAGE_PIN J20 [get_ports da_clk_ch2]

set_property PACKAGE_PIN U20 [get_ports da_pd_ch1]
set_property PACKAGE_PIN H20 [get_ports da_pd_ch2]
set_property IOSTANDARD LVCMOS33 [get_ports da_pd_ch1]
set_property IOSTANDARD LVCMOS33 [get_ports da_pd_ch2]

set_property SLEW FAST [get_ports ad_clk_ch1]
set_property SLEW FAST [get_ports da_clk_ch1]
set_property SLEW FAST [get_ports {da_data_ch1[*]}]
set_property SLEW FAST [get_ports ad_clk_ch2]
set_property SLEW FAST [get_ports da_clk_ch2]
set_property SLEW FAST [get_ports {da_data_ch2[*]}]

1.7 编译

Run Synthesis
Run Implementation
Generate Bitstream
编译发现2块ADA106超出资源，暂时只用了1块ADA106

1.8 导出 HDF

Vivado -> File -> Export -> Export Hardware -> 
-> Include bitstream -> OK

Vivado -> File -> Launch SDK -> OK 
得到 
linux_sd_adda/linux_sd_adda.sdk/hdmi_out_wrapper_hw_platform_0/system.hdf

下一篇：
petalinux_zynq7 C语言驱动DAC以及ADC模块之二https://blog.csdn.net/qq_27158179/article/details/136236138