题目：Always casez

Build a priority encoder for 8-bit inputs. Given an 8-bit vector, the output should report the first (least significant) bit in the vector that is 1. Report zero if the input vector has no bits that are high. For example, the input 8’b10010000 should output 3’d4, because bit[4] is first bit that is high.

• 为8位输入构建优先级编码器。给定一个8位向量，输出应该报告该向量中的第一个(最低有效)位为1。如果输入向量没有高位数，则报告零。例如，输入的8’b10010000应该输出3’d4，因为[4]是第一个高的位。

From the previous exercise (always_case2), there would be 256 cases in the case statement. We can reduce this (down to 9 cases) if the case items in the case statement supported don’t-care bits. This is what casez is for: It treats bits that have the value z as don’t-care in the comparison.

• 在前面的练习(always_case2)中，case语句中有256个case。如果case语句中的case项支持无关位，我们可以将其减少到9个case。这就是casez的作用:它在比较中将值为z的位视为不关心。

For example, this would implement the 4-input priority encoder from the previous exercise:

• 例如，这将实现前面练习中的4输入优先级编码器:

A case statement behaves as though each item is checked sequentially (in reality, a big combinational logic function). Notice how there are certain inputs (e.g., 4’b1111) that will match more than one case item. The first match is chosen (so 4’b1111 matches the first item, out = 0, but not any of the later ones).

• case语句的行为就像按顺序检查每个项一样(实际上是一个大的组合逻辑函数)。请注意，某些输入(例如，4’b1111)将匹配多个case项。选择第一个匹配项(因此4’b1111匹配第一个项，out = 0，但不匹配后面的任何项)。

There is also a similar casex that treats both x and z as don’t-care. I don’t see much purpose to using it over casez.

• 还有一种类似的情况，将x和z都视为不关心。我不觉得用它来代替casez有什么意义。

The digit ? is a synonym for z. so 2’bz0 is the same as 2’b?0

• 数字?是z的同义词，所以2’bz0和2’b是一样的?0

It may be less error-prone to explicitly specify the priority behaviour rather than rely on the ordering of the case items. For example, the following will still behave the same way if some of the case items were reordered, because any bit pattern can only match at most one case item:

• 显式指定优先级行为比依赖case项的顺序更不容易出错。例如，如果某些case项被重新排序，下面的代码仍然会以相同的方式运行，因为任何位模式最多只能匹配一个case项:
  

该题目给出了casez的使用方法。通过使用casez，可以将256个case，减少到9个。

// synthesis verilog_input_version verilog_2001
module top_module (
    input [7:0] in,
    output reg [2:0] pos  );
    always @(*) 
    casez (in)
        8'bzzzzzzz1: pos = 3’d0;   
        8'bzzzzzz10: pos = 3’d1;
        8'bzzzzz100: pos = 3’d2;
        8'bzzzz1000: pos = 3’d3;
        8'bzzz10000: pos = 3’d4;
        8'bzz100000: pos = 3’d5;
        8'bz1000000: pos = 3’d6;
        8'b10000000: pos = 3’d7;
        default: pos = 3’d0;
    endcase
endmodule