基本信号及概念

通信双方及通道

下图为edp规范中的总体框图。通过此框图我们可以了解到：

交互的双方：

1）source device 即 显卡的显示控制部分

2) sink device 即 显示屏

双方间的通道：

1） HPD 即热插拔，通过sink device 传递给source device。虽然有此信号，但是我们采用intel i915驱动支持的显卡，在实际测试过程中，热插拔edp后，connector的链接状态并没有发生变化，而且热插入后，通过modetest命令并不能查询到对应connector的信息。

2） aux channel，通过此通道可以控制背光、读取DPCD 信息以进行main-link的速率协商。

3） main-link ，即图像数据传输通道，支持的速率有：

• 1.62Gbps/lane (RBR)

• 2.7Gbps/lane (HBR)

• 5.4Gbps/lane (HBR2)

• 8.1Gbps/lane (HBR3）

支持的lane数目为x1 x2 x4

图1 EDP 框图

显示屏信号

图2 为某款显示屏的信号.

1. x2 lane 信号lane0 lan1

2. aux channel

3. HPD 信号

4. PWM 背光控制

此外这里除了EDID，还有timing-controller 通常缩写为TCON。

内核中EDP相关节点及配置

edp_swing

/sys/module/i915/parameters# cat edp_vswing

修改变量：

GRUB_CMDLINE_LINUX_DEFAULT="quiet splash i915.enable_psr=0 i915.edp_vswing=2"

修改完 /etc/default/grub ， 需要执行 sudo update-grub 生成 /boot/grub/grub.cfg，重启后生效

The parameter settings (after = sign) can be:

• 0=default, to do nothing

• 1=not sure, haven't found answer yet

• 2=control flicker, which OP used

工具命令

edid-decode

1）下载压缩包

apt download edid-decode

dpkg -x edid-decode_0.1~git20191209.e719d04-1build1_amd64.deb ./

2）使用

cat /sys/class/drm/card0-eDP-1/edid |./edid-decode

edid-decode (hex):

00 ff ff ff ff ff ff 00 09 d1 40 7b 36 02 00 00

23 1a 01 03 60 34 1d 78 2e 4e c0 a6 55 50 9c 26

11 50 54 af cf 00 d1 c0 b3 00 95 00 81 80 81 40

81 00 81 c0 71 40 02 3a 80 18 71 38 2d 40 58 2c

45 00 09 25 21 00 00 1e 00 00 00 fd 00 38 4b 1e

51 11 00 0a 20 20 20 20 20 20 00 00 00 fc 00 42

65 6e 51 20 56 5a 32 34 41 30 48 0a 00 00 00 ff

00 45 54 53 38 47 30 30 36 30 30 30 33 48 00 f5

---

EDID version: 1.3

Manufacturer: BNQ Model 31552 Serial Number 566

Made in week 35 of 2016

Analog display, Input voltage level: 0.7/0.7 V

Sync:

Maximum image size: 52 cm x 29 cm

Gamma: 2.20

DPMS levels: Off

RGB color display

Default (sRGB) color space is primary color space

First detailed timing is preferred timing

Color Characteristics

Red: 0.6494, 0.3320

Green: 0.3154, 0.6113

Blue: 0.1513, 0.0664

White: 0.3125, 0.3281

Established Timings I & II “Established Timings”（内建时序）表示显示器是否支持一些通用时序。

720x400 70.082 Hz 9:5 31.467 kHz 28.320 MHz (IBM)

640x480 59.940 Hz 4:3 31.469 kHz 25.175 MHz (DMT)

640x480 72.809 Hz 4:3 37.861 kHz 31.500 MHz (DMT)

640x480 75.000 Hz 4:3 37.500 kHz 31.500 MHz (DMT)

800x600 56.250 Hz 4:3 35.156 kHz 36.000 MHz (DMT)

800x600 60.317 Hz 4:3 37.879 kHz 40.000 MHz (DMT)

800x600 72.188 Hz 4:3 48.077 kHz 50.000 MHz (DMT)

800x600 75.000 Hz 4:3 46.875 kHz 49.500 MHz (DMT)

1024x768 60.004 Hz 4:3 48.363 kHz 65.000 MHz (DMT)

1024x768 70.069 Hz 4:3 56.476 kHz 75.000 MHz (DMT)

1024x768 75.029 Hz 4:3 60.023 kHz 78.750 MHz (DMT)

1280x1024 75.025 Hz 5:4 79.976 kHz 135.000 MHz (DMT)

Standard Timings

1920x1080 60.000 Hz 16:9 67.500 kHz 148.500 MHz (DMT)

1680x1050 59.954 Hz 16:10 65.290 kHz 146.250 MHz (DMT)

1440x900 59.887 Hz 16:10 55.935 kHz 106.500 MHz (DMT)

1280x1024 60.020 Hz 5:4 63.981 kHz 108.000 MHz (DMT)

1280x960 60.000 Hz 4:3 60.000 kHz 108.000 MHz (DMT)

1280x800 59.810 Hz 16:10 49.702 kHz 83.500 MHz (DMT)

1280x720 60.000 Hz 16:9 45.000 kHz 74.250 MHz (DMT)

1152x864 60.000 Hz 4:3 53.700 kHz 81.624 MHz (GTF)

Detailed mode: Clock 148.500 MHz, 521 mm x 293 mm

1920 2008 2052 2200 ( 88 44 148)

1080 1084 1089 1125 ( 4 5 36)

+hsync +vsync

VertFreq: 60.000 Hz, HorFreq: 67.500 kHz

Display Range Limits

Monitor ranges (GTF): 56-75 Hz V, 30-81 kHz H, max dotclock 170 MHz

Display Product Name: BenQ VZ24A0H

Display Product Serial Number: ETS8G0060003H

Checksum: 0xf5

====================

数据解析

1920 2008 2052 2200 ( 88 44 148) 水平

1080 1084 1089 1125 ( 4 5 36) 垂直

Horizontal: Active Time : 1920 Pixels Blanking Time : 280 Pixels Sync Offset : 88 Pixels Sync Pulse Width: 44 Pixels Border : 0 Pixels Frequency : 67 kHz Vertical: Active Time : 1080 Lines Blanking Time : 45 Lines Sync Offset : 4 Lines Sync Pulse Width: 5 Lines Border : 0 Lines

下角的Timing部分描述了时序的主要参数，含义见下表（软件显示有问题，参数名称显示不完整，表格中的参数也仅对应其在软件中的位置）。H Image、H Border、V Image、V Border几个参数一般用不到，表格中没有列出

intel_vbt_decode

apt install intel-gpu-tools

intel_vbt_decode /sys/kernel/debug/dri/0/i915_vbt

VBT header:

VBT signature: "$VBT SKYLAKE "

VBT version: 0x0064 (1.0)

VBT header size: 0x0030 (48)

VBT size: 0x10cc (4300)

VBT checksum: 0xfd

BDB offset: 0x00000030 (48)

BDB header:

BDB signature: "BIOS_DATA_BLOCK "

BDB version: 209

BDB header size: 0x0016 (22)

BDB size: 0x109c (4252)

BDB blocks present:

1 2 3 6 7 8 9 10 12 13 17 18 20 26 27 28

DPCD读取

cat /sys/kernel/debug/dri/0/eDP-1/i915_dpcd

ubuntu 20.4上这个节点不支持

Video BIOS Table (VBT)

The Video BIOS Table, or VBT, provides platform and board specific configuration information to the driver that is not discoverable or available through other means. By other means the most used method here is to read EDID table from the attached monitor, over Display Data Channel (DDC) using two pin I2C serial interface.

The VBT configuration is related to display hardware. The VBT is available via the ACPI OpRegion or, on older systems, in the PCI ROM (Option ROM).

The VBT consists of a VBT Header, a BIOS Data Block (BDB) Header, and a number of BIOS Data Blocks (BDBs) that contain the actual configuration information (supposed to replace the absence of EDID structure with the older monitors). The VBT Header, and thus the VBT, begins with “$VBT” signature. The VBT Header contains the offset of the BDB Header. The BDB header starts with the “BIOS_DATA_BLOCK” signature. The data blocks are concatenated after the BDB Header (not always in exact order, and certain BDBs might be missing, not implemented for such type of HW platforms). The data blocks have a 1-byte Block ID, 2-byte Block Size, and Block Size bytes of data (Block 53, the MIPI Sequence Block is an exception).

The GFX driver parses the VBT during load. The relevant information is stored in GFX driver private data for ease of use, and the actual VBT is not read after that.

为什么 在这里我们单独提及这个表呢? 这个表本身并不是针对EDP的，而是一个通用的配置，解决针对特定的硬件，需要调整的特定参数，例如v-swing及pre-emphasis 的调整都可以通过此表进行配置。

参考资料

Video BIOS Table (VBT) - L (liujunming.top)