目录
- 开发板介绍
- 下载仓库
- 工程设计
- 代码实现
- 工程构建
- 启动测试
- Memory测速
- Bootloader（裸机BareMetal程序）
- Bootloader（Linux OS）
- 开发板信息
开发板介绍
手头目前只有一个购买的BoChenK7开发板，后续会用它来进行LiteX FPGA SoC的构建
测试可能会包括：
- LED：【LiteX】【开发板】【BoChenK7】使用Python开发FPGA【Hello World、LED点灯、Memory测速、替换BIOS】
- DDR：本篇文章
- QSPI Flash
- SD Card
- Ethernet以太网
- HDMI视频输入输出
- PCIe
- Linux
下载仓库
LiteX有一个生态库叫做litex-boards，里面包含了上百种开发板（比如Xilinx、Digilent等品牌）
若是你手中有现成的开发板，可以直接使用litex-boards仓库：https://github.com/litex-hub/litex-boards
而我目前手头的是BoChenK7开发板我自己作了一个litex-boards-vacajk仓库：https://github.com/vacajk/litex-boards-vacajk
BoChenK7开发板在Python代码中的名称为：bochen_kintex7_base
litex-boards-vacajk仓库依赖LiteX开发环境，环境搭建方法可以跳转：【LiteX】使用Python实现FPGA SoC构建的开源工具
# 激活conda环境
conda activate <your conda env name>
# 进入litex环境目录
cd ~/Study/litex/env/litex
# 下载仓库
git clone git@github.com:vacajk/litex-boards-vacajk.git
# 安装仓库
cd litex-boards-vacajk
pip install --editable .
工程设计
bochen_kintex7_base开发板的基础配置文件：litex-boards-vacajk/litex_boards_vacajk/targets/bochen_kintex7_base.py
这次我们需要开启如下配置：
- --with-sdram
代码实现
源码：litex-boards-vacajk/litex_boards_vacajk/platforms/bochen_kintex7_base.py
- IO管脚约束
- DDR DCI_CASCADE约束
# _io = [
# DDR3 SDRAM
("ddram", 0,
Subsignal("a", Pins(
"AF8 AB10 V9 Y7 AC9 W8 Y11 V8",
"AA8 AC11 AD9 AA10 AF9 V7 Y8"),
IOStandard("SSTL15")),
Subsignal("ba", Pins("AA7 AB11 AF7"), IOStandard("SSTL15")),
Subsignal("ras_n", Pins("AD8"), IOStandard("SSTL15")),
Subsignal("cas_n", Pins("W10"), IOStandard("SSTL15")),
Subsignal("we_n", Pins("W9"), IOStandard("SSTL15")),
Subsignal("cs_n", Pins("AB7"), IOStandard("SSTL15")),
Subsignal("dm", Pins("AF15 AA15 AB19 V14"),
IOStandard("SSTL15")),
Subsignal("dq", Pins(
"AF14 AF17 AE15 AE17 AD16 AF20 AD15 AF19",
"AB15 AC14 AA18 AA14 AB16 AB14 AA17 AD14",
"AD19 AC19 AD18 AA19 AC17 AA20 AC18 AB17",
"Y17 V16 V17 W14 V18 W15 V19 W16"),
IOStandard("SSTL15_T_DCI")),
Subsignal("dqs_p", Pins("AE18 Y15 AD20 W18"),
IOStandard("DIFF_SSTL15")),
Subsignal("dqs_n", Pins("AF18 Y16 AE20 W19"),
IOStandard("DIFF_SSTL15")),
Subsignal("clk_p", Pins("AA9"), IOStandard("DIFF_SSTL15")),
Subsignal("clk_n", Pins("AB9"), IOStandard("DIFF_SSTL15")),
Subsignal("cke", Pins("AF10"), IOStandard("SSTL15")),
Subsignal("odt", Pins("AC8"), IOStandard("SSTL15")),
Subsignal("reset_n", Pins("Y10"), IOStandard("LVCMOS15")),
Misc("SLEW=FAST"),
Misc("VCCAUX_IO=HIGH")
),
# class Platform(Xilinx7SeriesPlatform):
# def do_finalize(self, fragment):
self.add_platform_command("set_property DCI_CASCADE {{32}} [get_iobanks 33]")
源码：litex-boards-vacajk/litex_boards_vacajk/targets/bochen_kintex7_base.py
- SDRAM需要4倍于系统时钟频率的时钟
- SoC及总线运行在100MHz
- SDRAM的bitrate为800Mbps（DDR数据，需要800/2=400MHz的时钟）
- 添加DDR3 PHY：s7ddrphy.K7DDRPHY
- 添加SDRAM模块：self.add_sdram
# class _CRG(LiteXModule):
if with_sdram:
self.cd_sys4x = ClockDomain()
pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
# class BaseSoC(SoCCore):
# DDR3 SDRAM -------------------------------------------------------------------------------
if with_sdram and not self.integrated_main_ram_size:
self.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"),
memtype = "DDR3",
nphases = 4,
sys_clk_freq = sys_clk_freq)
self.add_sdram("sdram",
phy = self.ddrphy,
module = MT41K256M16(sys_clk_freq, "1:4"),
l2_cache_size = kwargs.get("l2_size", 8192),
)
工程构建
# 加载vivado开发环境
$ source ~/Xilinx/Vitis/2021.1/settings64.sh
# 找一个工程目录（如果使用python -m的方法，在哪里运行都无所谓）
$ cd ~/Study/litex/env/litex-boards-vacajk/litex_boards_vacajk
# 编译BIOS、综合、布局、布线、生成bitstream
$ python -m litex_boards_vacajk.targets.bochen_kintex7_base --with-sdram --build
启动测试
连接JTAG(USB)、UART(USB)、电源(USB)到BoChenK7开发板
# 查看USB转串口设备名
$ ls /dev/ttyUSB*
/dev/ttyUSB0
# +x属性到USB转串口设备
$ sudo chmod +x /dev/ttyUSB0
提前打开新的BASH Shell，使用litex_term打开串口监听
# BASH B
$ cd ~/Study/litex/env/litex-boards-vacajk/litex_boards_vacajk
$ litex_term /dev/ttyUSB0
打开litex_term后，再进行FPGA bitstream下载
# BASH A
$ cd ~/Study/litex/env/litex-boards-vacajk/litex_boards_vacajk
$ python -m litex_boards_vacajk.targets.bochen_kintex7_base --with-sdram --load
查看BASH B中的litex_term命令行
__ _ __ _ __
/ / (_) /____ | |/_/
/ /__/ / __/ -_)> <
/____/_/\__/\__/_/|_|
Build your hardware, easily!
(c) Copyright 2012-2024 Enjoy-Digital
(c) Copyright 2007-2015 M-Labs
BIOS built on Aug 17 2024 21:40:22
BIOS CRC passed (be79585d)
LiteX git sha1: 35498b468
--=============== SoC ==================--
CPU: VexRiscv @ 100MHz
BUS: wishbone 32-bit @ 4GiB
CSR: 32-bit data
ROM: 128.0KiB
SRAM: 8.0KiB
L2: 8.0KiB
SDRAM: 1.0GiB 32-bit @ 800MT/s (CL-6 CWL-5)
MAIN-RAM: 1.0GiB
--========== Initialization ============--
Initializing SDRAM @0x40000000...
Switching SDRAM to software control.
Write leveling:
tCK equivalent taps: 32
Cmd/Clk scan (0-16)
|1111111111100000| best: 0
Setting Cmd/Clk delay to 0 taps.
Data scan:
m0: |000000001111111111111111| delay: 08
m1: |000000001111111111111111| delay: 08
m2: |000000000001111111111111| delay: 11
m3: |000000000011111111111111| delay: 10
Write latency calibration:
m0:0 m1:0 m2:0 m3:0
Write DQ-DQS training:
m0: |011111111111111100000000000000000| delays: 07+-06
m1: |011111111111111100000000000000000| delays: 07+-06
m2: |000011111111111111100000000000000| delays: 10+-06
m3: |000111111111111111000000000000000| delays: 09+-06
Read leveling:
m0, b00: |00000000000000000000000000000000| delays: -
m0, b01: |00011111111111111000000000000000| delays: 09+-06
m0, b02: |00000000000000000000111111111111| delays: 25+-05
m0, b03: |00000000000000000000000000000000| delays: -
m0, b04: |00000000000000000000000000000000| delays: -
m0, b05: |00000000000000000000000000000000| delays: -
m0, b06: |00000000000000000000000000000000| delays: -
m0, b07: |00000000000000000000000000000000| delays: -
best: m0, b01 delays: 09+-06
......
best: m3, b01 delays: 08+-07
Switching SDRAM to hardware control.
Memtest at 0x40000000 (2.0MiB)...
Write: 0x40000000-0x40200000 2.0MiB
Read: 0x40000000-0x40200000 2.0MiB
Memtest OK
Memspeed at 0x40000000 (Sequential, 2.0MiB)...
Write speed: 58.2MiB/s
Read speed: 62.4MiB/s
--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found
--============= Console ================--
litex>
可以看到BIOS启动时：
- 驱动对SDRAM进行了初始化（包括了各种IO delay训练）
- 初始化完成后将SDRAM的控制权交给了硬件
- 对SDRAM进行了读写速度测试
- 写：58.2MB/s
- 读：62.4MB/s
Memory测速
litex> help
sdram_mr_write - Write SDRAM Mode Register
sdram_force_bitslip - Force write leveling Bitslip
sdram_rst_bitslip - Reset write leveling Bitslip
sdram_force_dat_delay - Force write leveling Dat delay
sdram_rst_dat_delay - Reset write leveling Dat delay
sdram_cal - Calibrate SDRAM
sdram_test - Test SDRAM
sdram_init - Initialize SDRAM (Init + Calibration)
sdram_force_cmd_delay - Force write leveling Cmd delay
sdram_rst_cmd_delay - Reset write leveling Cmd delay
sdram_force_wrphase - Force write phase
sdram_force_rdphase - Force read phase
litex> mem_list
Available memory regions:
ROM 0x00000000 0x20000
SRAM 0x10000000 0x2000
MAIN_RAM 0x40000000 0x40000000
CSR 0xf0000000 0x10000
litex> sdram_test
Memtest at 0x40000000 (32.0MiB)...
Write: 0x40000000-0x42000000 32.0MiB
Read: 0x40000000-0x42000000 32.0MiB
Memtest OK
litex> mem_speed 0x40000000 0x20000
Memspeed at 0x40000000 (Sequential, 128.0KiB)...
Write speed: 58.1MiB/s
Read speed: 59.4MiB/s
Bootloader（裸机BareMetal程序）
编译demo程序
# --build-path=build/bochen_kintex7_base：指向编译目录，该文件夹中包含了gateware和software子目录
$ cd ~/Study/litex/env/litex-boards-vacajk/litex_boards_vacajk
$ litex_bare_metal_demo --build-path=build/bochen_kintex7_base
提前打开新的BASH Shell，使用litex_term打开串口监听，并指定bootloader需要下载的二阶段启动程序demo.bin
# BASH B
$ cd ~/Study/litex/env/litex-boards-vacajk/litex_boards_vacajk
# --kernel <kernel image>：可以是bare metal程序，也可以是Linux的uboot
$ litex_term /dev/ttyUSB0 --kernel demo.bin
打开litex_term后，再进行FPGA bitstream下载
# BASH A
$ cd ~/Study/litex/env/litex-boards-vacajk/litex_boards_vacajk
$ python -m litex_boards_vacajk.targets.bochen_kintex7_base --load
在BASH B中查看demo.bin的加载和运行
--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
[LITEX-TERM] Received firmware download request from the device.
[LITEX-TERM] Uploading demo.bin to 0x40000000 (7556 bytes)...
[LITEX-TERM] Upload calibration... (inter-frame: 10.00us, length: 64)
[LITEX-TERM] Upload complete (9.8KB/s).
[LITEX-TERM] Booting the device.
[LITEX-TERM] Done.
Executing booted program at 0x40000000
--============= Liftoff! ===============--
LiteX minimal demo app built Aug 17 2024 21:59:56
Available commands:
help - Show this command
reboot - Reboot CPU
led - Led demo
donut - Spinning Donut demo
helloc - Hello C
litex-demo-app> helloc
Hello C demo...
C: Hello, world!
litex-demo-app> led
Led demo...
Counter mode...
Shift mode...
Dance mode...
litex-demo-app> donut
Donut demo...
$$@@@@@@@$
##########$$$$@@@$
##**!!!!!!!!**###$$$$$$#
***!!!;;;==;=!=!!**##$$$$$$*
**!===;;::~:::;;==!**####$$$#*
!!!=;;:~-,,.,--::;==!**########*
!!!!=;:-,......,-~:;=!!***######*!
!!*!==:~-,........-:;=!!!**######*!
!**!!=;:~,... .,~;==!!****##***!=
;!*#####*!=. -:;==!!!********!==
;!##$$$$$$#!- :;===!!!*******!!!=;
:=*#$$@@@@$$#*=====!!!!!*****!*!!!=;
=!*#$$@@@@$$#***!!!!!!!***!!!!!!=;:
:=!*##$$$$$##*******!!!!!!!!!!==;:
:=!***######******!!!!!!!!===;;:
:=!!!!********!!!!!!!!===;;::-
-:==!!=!!!!!!!!!=====;;;::~,
,::;;========;=;;;:::~-.
.,~~:::::::::~~~-,.
litex-demo-app>
在命令行中我们可以看到：
- BIOS启动
- 初始化SDRAM
- 对SRAM和SDRAM进行了读写测试
- 从串口加载Kernel程序
- 从SDRAM启动demo.bin程序
- 手动输入命令对demo程序进行了测试，包括：
- helloc
- led
- donut
Bootloader（Linux OS）
TODO：待补充
开发板信息
BoChenK7开发板的接口如下图，还是比较丰富的
![[算法题]【模板】前缀和/【模板】二维前缀和](https://i-blog.csdnimg.cn/direct/d09d8d0239694cc2a1648a1b5459e877.png)
