一.FPGA基础
1.FPGA烧录流程
(1) 加载流文件 —— bitfile
(2) 烧录文件 —— cmm
二.MMC
1.基础知识
(1)jz4740、mmc、emmc、sd之间的关系？
jz4740——处理器
mmc——存储卡标准
emmc——mmc基础上发展的高效存储解决方案
sd——
三.eMMC和SD case验证
1.case(以eMMC为例)
(1) PIO模式：PIO（编程输入/输出）模式涉及CPU直接参与内存与eMMC设备之间的数据传输。数据由CPU负责控制数据从eMMC设备到内存的运输，这对于大量数据传输来说效率不高，因为它消耗了大量的CPU资源；
(2) SDMA模式：SDMA（单数据速率模式访问）模式使用直接内存访问（DMA），不需要CPU干预即可传输数据，从而释放了CPU。这比PIO更有效率，适用于更大的数据传输；
(3) ADMA模式：ADMA（高级DMA）模式是为存储设备（如SD卡和eMMC卡）设计的一种增强型DMA，专门用于高性能数据传输。它支持更复杂的散点聚集型操作，其中数据可以非连续地传输；
(4) DMA突发大小：这指的是eMMC控制器在使用DMA时一次突发中可以传输的数据量。更大的突发大小可以提高数据传输效率，但要求控制器和内存支持这些大小；
(5) HS/HS200/HS400es模式：这些是eMMC设备支持的高速模式：
a,HS(高速):比默认速度运行频率更高，以增加数据传输速率；
b,HS200：一种高速模式，操作速度为200 MB/s；
c,HS400es：更快的模式，能够达到最高400 MB/s，常用于较新和更先进的设备中；
(6) CQE：命令队列引擎。此功能允许eMMC设备接受多个命令在一个队列中，然后可以重新排序并最优化执行以提高性能。它与SCSI和 SATA等其他存储技术中的命令队列类似。
(7) Clock频点：指的是eMMC时钟的操作频率；更高的时钟频率可以增加数据传输速度，但也需要更大的功耗并可能产生更多热量。
(8) ICE：内联加密引擎，用于硬件基础上加密和解密存储在eMMC上的数据。这允许在不显著增加CPU负担的情况下，安全存储和传输数据；
(9) 通用：寄存器值确认：这可能是指验证eMMC设备配置寄存器中的值的实践。这些寄存器控制eMMC的各种操作参数，确认它们的值对于调试、初始配置和确保稳定运行非常重要。
2.PIO和DMA
(1) PIO——PIO模式是一种数据传输模式(技术)，每次数据传输都需要CPU直接介入，CPU必须从输入/输出端口读取数据并将其移动到内存
(2) DMA——一种使外围设备能够直接向系统内存读写数据的数据传输技术，无需CPU的直接介入
DMA基础知识
3.存储器
存储器相关
(1) 缓存
(2) 主存
(3) 辅存
4.代码块
(1) lark-fpga.dts // 修改代码参数
// 设备节点名称，表示AXI总线地址
axi@d4200000 {
/* eMMC */
// 设备节点名称，表示SD卡控制器设备
sdh2: sdh@d4271000 {
// SD卡控制器的总线宽度为8位
bus-width = <8>;
// SD卡固定在设备上
non-removable;
// 支持CQE
supports-cqe;
// 支持内联加密
supports-inlinecrypt;
// 支持高速的eMMC模式
cap-mmc-highspeed;
// SD卡控制器不支持SD卡
no-sd;
// SD卡控制器不支持SDIO功能
no-sdio;
// SD卡控制器的特殊行为1
asr,sdh-quirks = <(
SDHCI_QUIRK_BROKEN_CARD_DETECTION |
SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
)>;
// SD卡控制器的特殊行为2
asr,sdh-quirks2 = <(
SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
SDHCI_QUIRK2_BROKEN_HS200 |
SDHCI_QUIRK2_BROKEN_PHY_MODULE
)>;
// 工作频率375MHz
asr,sdh-freq = <375000000>;
status = "okay";
};
(2) sdhci.h //sdh-quirk定义
/* Controller doesn't honor resets unless we touch the clock register */
#define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0)
/* Controller has bad caps bits, but really supports DMA */
#define SDHCI_QUIRK_FORCE_DMA (1<<1)
/* Controller doesn't like to be reset when there is no card inserted. */
#define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<2)
/* Controller doesn't like clearing the power reg before a change */
#define SDHCI_QUIRK_SINGLE_POWER_WRITE (1<<3)
/* Controller has an unusable DMA engine */
#define SDHCI_QUIRK_BROKEN_DMA (1<<5)
/* Controller has an unusable ADMA engine */
#define SDHCI_QUIRK_BROKEN_ADMA (1<<6)
/* Controller can only DMA from 32-bit aligned addresses */
#define SDHCI_QUIRK_32BIT_DMA_ADDR (1<<7)
/* Controller can only DMA chunk sizes that are a multiple of 32 bits */
#define SDHCI_QUIRK_32BIT_DMA_SIZE (1<<8)
/* Controller can only ADMA chunks that are a multiple of 32 bits */
#define SDHCI_QUIRK_32BIT_ADMA_SIZE (1<<9)
/* Controller needs to be reset after each request to stay stable */
#define SDHCI_QUIRK_RESET_AFTER_REQUEST (1<<10)
/* Controller needs voltage and power writes to happen separately */
#define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER (1<<11)
/* Controller provides an incorrect timeout value for transfers */
#define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL (1<<12)
/* Controller has an issue with buffer bits for small transfers */
#define SDHCI_QUIRK_BROKEN_SMALL_PIO (1<<13)
/* Controller does not provide transfer-complete interrupt when not busy */
#define SDHCI_QUIRK_NO_BUSY_IRQ (1<<14)
/* Controller has unreliable card detection */
#define SDHCI_QUIRK_BROKEN_CARD_DETECTION (1<<15)
/* Controller reports inverted write-protect state */
#define SDHCI_QUIRK_INVERTED_WRITE_PROTECT (1<<16)
/* Controller has unusable command queue engine */
#define SDHCI_QUIRK_BROKEN_CQE (1<<17)
/* Controller does not like fast PIO transfers */
#define SDHCI_QUIRK_PIO_NEEDS_DELAY (1<<18)
/* Controller does not have a LED */
#define SDHCI_QUIRK_NO_LED (1<<19)
/* Controller has to be forced to use block size of 2048 bytes */
#define SDHCI_QUIRK_FORCE_BLK_SZ_2048 (1<<20)
/* Controller cannot do multi-block transfers */
#define SDHCI_QUIRK_NO_MULTIBLOCK (1<<21)
/* Controller can only handle 1-bit data transfers */
#define SDHCI_QUIRK_FORCE_1_BIT_DATA (1<<22)
/* Controller needs 10ms delay between applying power and clock */
#define SDHCI_QUIRK_DELAY_AFTER_POWER (1<<23)
/* Controller uses SDCLK instead of TMCLK for data timeouts */
#define SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK (1<<24)
/* Controller reports wrong base clock capability */
#define SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN (1<<25)
/* Controller cannot support End Attribute in NOP ADMA descriptor */
#define SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC (1<<26)
/* Controller is missing device caps. Use caps provided by host */
#define SDHCI_QUIRK_MISSING_CAPS (1<<27)
/* Controller uses Auto CMD12 command to stop the transfer */
#define SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 (1<<28)
/* Controller doesn't have HISPD bit field in HI-SPEED SD card */
#define SDHCI_QUIRK_NO_HISPD_BIT (1<<29)
/* Controller treats ADMA descriptors with length 0000h incorrectly */
#define SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC (1<<30)
/* The read-only detection via SDHCI_PRESENT_STATE register is unstable */
#define SDHCI_QUIRK_UNSTABLE_RO_DETECT (1<<31)
5.语法基础
if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
(host->flags & SDHCI_USE_ADMA)) {
DBG("Disabling ADMA as it is marked broken\n");
host->flags &= ~SDHCI_USE_ADMA;
}
(1) &= 按位与
(2) ~ 取反
