学习:

Your circuit has one 16-bit input, and four outputs. Build this circuit that recognizes these four scancodes and asserts the correct output.

To avoid creating latches, all outputs must be assigned a value in all possible conditions (See also always_if2). Simply having a default case is not enough. You must assign a value to all four outputs in all four cases and the default case. This can involve a lot of unnecessary typing. One easy way around this is to assign a "default value" to the outputs before the case statement:

always @(*) begin
    up = 1'b0; down = 1'b0; left = 1'b0; right = 1'b0;
    case (scancode)
        ... // Set to 1 as necessary.
    endcase
end

This style of code ensures the outputs are assigned a value (of 0) in all possible cases unless the case statement overrides the assignment. This also means that a default: case item becomes unnecessary.

Reminder: The logic synthesizer generates a combinational circuit that behaves equivalently to what the code describes. Hardware does not "execute" the lines of code in sequence.

译:

你的电路有一个16位的输入和四个输出。构建这个电路，它能识别这四个扫描码，并断言正确的输出。

为了避免产生锁存器，所有输出必须在所有可能的条件中被赋值（另见always_if2）。仅仅有默认情况是不够的。你必须在所有四种情况和默认情况下为所有四个输出赋值。这可能涉及大量的不必要输入。解决这个问题的一个简单方法是在case语句之前为输出分配一个“默认值”。

这种编码风格确保了除非case语句覆盖了赋值，否则在所有可能的情况下输出都会被赋值为0。这也意味着默认的case项变得不再必要。

提醒：逻辑综合器生成的组合电路行为与代码描述的等效。硬件不会按顺序“执行”代码行。

// synthesis verilog_input_version verilog_2001
module top_module (
    input [15:0] scancode,
    output reg left,
    output reg down,
    output reg right,
    output reg up  ); 
always @(*) begin
    up = 1'b0; down = 1'b0; left = 1'b0; right = 1'b0;
    case (scancode)
        16'he06b: left = 1'b1; // Set to 1 as necessary.
        16'he072: down = 1'b1;
        16'he074: right = 1'b1;
        16'he075: up = 1'b1;
    endcase
end
endmodule

运行结果:

        

分析:

        本题意为在有多路默认值需要配置的时候的方法