专栏前言

本专栏的内容主要是记录本人学习Verilog过程中的一些知识点，刷题网站用的是牛客网

`timescale 1ns/1ns

module clk_divider
    #(parameter dividor = 5)
( 	input clk_in,
	input rst_n,
	output clk_out
);

	parameter CNT_WIDTH = $clog2(dividor - 1) ; 
	reg flag1, flag2 ; 
	reg [CNT_WIDTH:0] cnt ; 

	always @ (posedge clk_in or negedge rst_n) 
		if (!rst_n) cnt <= 0 ; 
		else cnt <= cnt == dividor - 1 ? 0 : cnt + 1 ; 
	
	always @ (posedge clk_in or negedge rst_n) 
		if (!rst_n) flag1 <= 0 ; 
		else if (cnt == (dividor - 1) >> 1) flag1 <= ~flag1 ; 
		else if (cnt == dividor - 1) flag1 <= ~flag1 ; 
		else flag1 <= flag1 ; 
	
	always @ (negedge clk_in or negedge rst_n) 
		if (!rst_n) flag2 <= 0 ; 
		else if (cnt == (dividor - 1) >> 1) flag2 <= ~flag2 ; 
		else if (cnt == dividor - 1) flag2 <= ~flag2 ; 
		else flag2 <= flag2 ; 

	assign clk_out = flag1 || flag2 ;

endmodule