内容：

给cpubank写testbench:

1.the testbench have test a variety of operations the sequence described:
i) Reset: The test bench should first reset the register bank. The reset is synchronous. It
should also set rrd1, rrd2, d, rwr, rwren to zero.
ii) Store1: store the value 0x55 to register RA
iii) Store2: store the value 0xAA to register RB
iii) Store3: store the value 0xFF to register RC
iv) Load1: get the content of register RA on q1 and RB on q2
v) Load2: get the content of register RC on q1 and RD on q2
the tb is this:

Generate clk simulation:
proc_stim_clk: process
begin
clk<=‘0’;
wait for 50ns;
clk<=‘1’;
wait for 50ns;
end process;

Generate the process for store for RA,RB and RC:
proc_stim_rst: process
begin
rst<=‘1’;