FPGA实现数码管显示分秒时间

news2025/4/26 7:30:40

一. verilog实现

二. 烧录验证

三. 结果验证

使用开发板：DE2-115开发板

一. verilog实现

要实现分和秒，需要知道定时器的频率，通过查手册可知，我使用的开发板时钟为50hz，也就是时钟一个周期是2微秒。

$50000000\cdot 2\mu s=1s$

50000000需要用一个26位的寄存器保存

我们要依次实现秒和分

所以我们可以写出以下代码实现

module time_show1(
    input  clk,
	 input  Rst,
	 input  Pause,
    output reg [7:0] seg1,
	 output reg [6:0] seg2,
	 output reg [6:0] seg3,
	 output reg [6:0] seg4
);
reg [25:0] count1;
reg [5:0] count2;
reg [5:0] count3;
reg [5:0] count4;
reg [5:0] count5;
always@(posedge clk or posedge Rst)begin
    if(Rst) begin  
        // 复位所有计数器
        count1 <= 26'd0;
        count2 <= 6'd0;
        count3 <= 6'd0;
        count4 <= 6'd0;
        count5 <= 6'd0;
    end
	 else begin
	 if(!Pause)begin
		count1<=count1+1;
	 end
	 count1 <= count1+1;
    if(count1>50_000_000-2)begin
        count1<=0; 
        count2<=count2+1;   
    end
	 if(count2==10)begin
		count2<=0;
		count3<=count3+1;
	 end
	 if(count3==6&&count2==0)begin
		count3<=0;
		count4<=count4+1;
	 end
	 if(count4==10)begin
		count4<=0;
		count5<=count5+1;
	 end
	 if(count5==6&&count4==0)begin
		count5<=0;
	 end
	 end
end

always@(*)begin
	case(count2)
		0:seg1 <= 8'b0100_0000;
		1:seg1 <= 8'b0111_1001;
		2:seg1 <= 8'b0010_0100;
		3:seg1 <= 8'b0011_0000;
		4:seg1 <= 8'b0001_1001;
			
		5:seg1 <= 8'b0001_0010;
		6:seg1 <= 8'b0000_0010;
		7:seg1 <= 8'b0111_1000;
		8:seg1 <= 8'b0000_0000;
		9:seg1 <= 8'b0001_1000;
	default:seg1<=8'b0111_1111;//输入有误时默认值
	endcase
	case(count3)
		0:seg2 <= 8'b100_0000;
		1:seg2 <= 8'b111_1001;
		2:seg2 <= 8'b010_0100;
		3:seg2 <= 8'b011_0000;
		4:seg2 <= 8'b001_1001;
			
		5:seg2 <= 8'b001_0010;
		6:seg2 <= 8'b000_0010;
		7:seg2 <= 8'b111_1000;
		8:seg2 <= 8'b000_0000;
		9:seg2 <= 8'b001_1000;
	default:seg2<=8'b111_1111;//输入有误时默认值
	endcase
	case(count4)
		0:seg3 <= 8'b100_0000;
		1:seg3 <= 8'b111_1001;
		2:seg3 <= 8'b010_0100;
		3:seg3 <= 8'b011_0000;
		4:seg3 <= 8'b001_1001;
			
		5:seg3 <= 8'b001_0010;
		6:seg3 <= 8'b000_0010;
		7:seg3 <= 8'b111_1000;
		8:seg3 <= 8'b000_0000;
		9:seg3 <= 8'b001_1000;
	default:seg3<=8'b111_1111;//输入有误时默认值
	endcase
	case(count5)
		0:seg4 <= 8'b100_0000;
		1:seg4 <= 8'b111_1001;
		2:seg4 <= 8'b010_0100;
		3:seg4 <= 8'b011_0000;
		4:seg4 <= 8'b001_1001;
			
		5:seg4 <= 8'b001_0010;
		6:seg4 <= 8'b000_0010;
		7:seg4 <= 8'b111_1000;
		8:seg4 <= 8'b000_0000;
		9:seg4 <= 8'b001_1000;
	default:seg4<=8'b111_1111;//输入有误时默认值
	endcase
end
endmodule