本文作为SpinalHDL学习笔记第六十六篇，介绍SpinalHDL的VHDL例化和Verilog IP(Instantiate VHDL and Verilog IP)。
目录：
1.描述(Description)
2.定义⿊盒(Defining an blackbox)
3.范式(Generics)
4.例化⿊盒(Instantiating a blackbox)
5.时钟和复位的布局(Clock and reset mapping)
6.io前缀(io prefix)
7.重命名⿊盒的所有io(Rename all io of a blackbox)
8.添加RTL源(Add RTL source)
9.VHDL——非数字类型(VHDL-No numeric type)
⼀、描述(Description)
⿊盒(blackbox)允许使⽤者把已有的VHDL/Verilog模块通过指定接⼝集成到当前设计中, 这种调⽤的正确描述取决于仿真器或综合器。
⼆、定义⿊盒(Defining an blackbox)
⼀个定义⿊盒的例⼦如下所⽰：
/定义Ram⿊盒
class Ram_1w_1r(wordWidth: Int, wordCount: Int) extends BlackBox {
//给⿊盒增加VHDL范式/Verilog参数
//你可以⽤String, Int, Double, Boolean和所有基于SpinalHDL的类型作为参数值
addGeneric("wordCount", wordCount)
addGeneric("wordWidth", wordWidth)
//定义VHDL通道的io/Verilog模块
val io = new Bundle {
val clk = in Bool()
val wr = new Bundle {
val en = in Bool()
val addr = in UInt(log2Up(wordCount) bits)
val data = in Bits(wordWidth bits)
}
val rd = new Bundle {
val en = in Bool(
