专栏前言

本专栏的内容主要是记录本人学习Verilog过程中的一些知识点，刷题网站用的是牛客网

`timescale 1ns/1ns

module det_moore(
   input                clk   ,
   input                rst_n ,
   input                din   ,
 
   output	reg         Y   
); 
    parameter S0 = 0, S1 = 1 , S2 = 2, S3 = 3, S4 = 4 ;
    reg [2:0] nstate, state ; 

    always @ (posedge clk or negedge rst_n) 
        if (!rst_n) state <= S0 ; 
        else state <= nstate ; 

    always @ (*) 
        case (state) 
            S0 : nstate = din ? S1 : S0 ; 
            S1 : nstate = din ? S2 : S0 ; 
            S2 : nstate = din ? S2 : S3 ;
            S3 : nstate = din ? S4 : S0 ; 
            S4 : nstate = din ? S1 : S0 ; 
            default : nstate = S0 ;
        endcase

    always @ (posedge clk or negedge rst_n) 
        if (!rst_n) Y <= 0 ; 
        else if (state == S4) Y <= 1 ; 
        else Y <= 0 ; 

endmodule